>>WHen Tom's Reviews DDR SDRAM,
>>for instance in the mainboard guide,
>>He said he used:
>>256 MB Infineon PC 2100 DDR SDRAM 8-8-5-2-2-2-2.
>>WHat does 8-8-5-2-2-2-2 mean? ( I understand the rest )
>>When Tom's Reviews PC 133 SDRAM he says
>>256 MB Wichman WorkX PC133 SDRAM 2-2-2-5/7
>>What does 2-2-2-5/7
>>RAS-CAS-?-?/?
The numbers 8-8-5-2-2-2-2 relate to the memory timing setting on AMD 761 Northbridge. Listed in their respective order, they are;
SDRAM Page Hit Limit
Because under normal operation conditions, there is only a limited probability that the next read command will hit the same page as the previous one, chances for a page miss increase exponentially after each consecutive page hit. In case, the page is still open, this means that it needs to be closed first before another row select command can be issued. Therefore, it is better to force a page closing after a certain number of page hits. This will shave off the number of latency cycles required for a Precharge (tPR) from the overall page miss latencies. For gaming applications with a high locality of data, the best performance will be achieved by setting this entry to the maximum value of 16, which will further increase stability.
SDRAM Idle Limit
This setting relates to the Page Hit Limit. Because there is not only a spatial constraint on how many consecutive hits can go to the same page but, moreover, a temporal component as well, the controller can be programmed to close a page if there have been no read requests in a given number of bus cycles. Recommended setting: 8 cycles
SDRAM tRC Timing Value
The minimum time between two consecutive accesses of the same bank. Parameters needed to be taken into account are tRCD and CAS latency as well as Precharge (tRP) (see below). As a rule of thumb, tRC should be set such that it is the sum of tRAS and tRP.
SDRAM tRP Timing Value
When a bank is open and a page miss occurs, the bank needs to be closed before the next bank activate command can be issued. Electrically, this is done by resetting the RAS lines to neurtral by means of a precharge that erases all information accumulated as function of the last bank activate command. In most cases, 2 cycles are enough, for higher speed, 3 cycles are recommended.
SDRAM tRAS
tRAS is the RAS pulse width, that is the time required for the bit-lines to build up the voltage potential necessary for restoring the data to the memory cells of origin. Setting tRAS too short will eventually cause data corruption not only in the memory array but can also cause hard drive corruption. Historically, tRAS was defined as the sum of tRCD and CAS latency, however, with the current high speed DRAMs, this equation no longer holds. As a rule of thumb, at 100 MHz memory bus speed (200 MHz data rate) a tRAS of 5 cycles suffices in most cases. At or above 133 MHz using tRAS of less than 6 is like playing Russian Roulette. tRAS has little or no impact on performance unless software is used that causes totally random accesses.
SDRAM tRCD and CAS latency
CAS latency is the most important parameter for system performance, RAS-TO-CAS Delay is secondary but the parameter hardest to keep short in current DRAM designs.
As for the 2-2-2-5/7 setting, they refer to SDRAM CAS Latency(2 or 3), SDRAM RAS TO CAS Delay(2 or 3), SDRAM RAS Precharge time(2 or 3)and SDRAM Cycle time(5/7 or 7/9).
Hope that helps.
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