Another THG cock-up

McEwin

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Dec 31, 2007
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Here is a quote from the conclusion of the "behind the silicon curtain" review:

"Our benchmark results clearly prove that if Intel changes the FSB and memory clocks (to 133 MHz and 533 MHz, respectively), this will put it quite a distance ahead of its competition from AMD, as well as its own series of processors"

The benchmarks DO NOT prove this point WHAT SO EVER. The clock frequencies of all the Intel processors with the 133MHz bus are considerably higher than the currently available processors. So it only proves that the these future processors run faster than current.

To PROVE the above quotation you would have to benchmark the CPUs (with different FSB/memory) at the same clock frequencies.

McEwin
 

FatBurger

Illustrious
Good eye, I bet the authors would be more interested in your comments than I would, though :tongue:

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eden

Champion
Actually I'd like to see clock per clock how much it has improved. Just for fun though, it's not like it has outperformed the AXP but to see how much exactly it improved!

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FatBurger

Illustrious
I wouldn't mind either, but there's nothing you or I (or any other members of the forum) can do to persuade THG to write such an article, that a well-written email could not do just as easily, and more effectively.

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girish

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well, that seems to be a hangover of FSB speeds and memory transfers, the days when they actually mattered.

but today it seems they have come to a point that they are simply too much for today's CPUs to handle. the classic example is the P4 (which would possibly the only future intel processor or at least its bus) which even at 3.2 GB/sec (forget the actual FSB MHz) sucks! its in its design (the deep deep hyperpipeline!) that it cannot really make much use of the available memory bandwidth with mainstream applications which are in fact what the people will use. making it 4.2 GB with 533(133x4) MHz would not improve the performance by that proportion of 25%, far from it!

what could improve hoever is the L2 cache, which should improve the performance of all processor in general, but how much the P4 in particular has gained? A larger L2 cache is effectively same as increasing the memory bandwidth since it is the one through which all memory requirements of the processors since handled and the larger L2 does get more bytes per second to the CPU core than a smaller one.

so if anybody thinks that the P4 handles 20 instructions per cycle they are correct, technically. but if they think it means it can execute 20 instructions per second, they are wrong. instructions per second is still the same as number of pipes/execution units and that too subject to the quality of code!

girish

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girish

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actually, all the current processor work with 133 MHz physical frequency, and double or quadruple it by certain configurational tricks.

what really matters is performance, which these days is not the single function of MHz, a faster processor with raw MHz does not necessary means better performance. see the P4!

I am amused at the statement guys at THG have made. they dont seem to remember that the Athlons and C3s are already runnng at 133 MHz and 266 MHz FSBs, and that the 400 MHz FSB of P4 is not that beneficial to it given the architecture. maybe sometime in future the P4 will improve, its a new design and needs to mature.

interesting that intel is putting the 400/533 MHz quad pumped FSB on all its processors ranging from value desktop celerons, mainstream P4s and server P4 Xeons! the FSB is good, now we need a better core to actually utilise it.

girish

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