pc 2700 damn Djungle out there

ShadeK

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Mar 27, 2002
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18,510
Ok here is the deal.
Im gonna buy me some sweet PC2700 (DDR333) memorys.
My idea was getting 2 x 512mems, all good with that and all.
But its a damn Djungle out there...
What brand should i go for?
I found this test once there they tested this new memorys.
But i lost it..
Anyways to get to the point.
Anyone have a andress to a website with a test or anyone know anything about these mems. I dont whanna spend a fortune and get some sh!t.

i found some 512 PC2700 (DDR333) from samsung.
then I found another brand that only cost half the price.
whats up with that...!! no idea.

I would sure like some help. ThanX

replys in swedish works fine

/ShadeK
 

ShadeK

Distinguished
Mar 27, 2002
8
0
18,510
the other mems where named
"DDR 512MB PC2700 orig DIMM 184-pin, DDR333" or somethign like that and i couldnt get any detailed informationg about em
the samsung had alot of detailed fact.. but im not really into memory terms so they dont tell me that much actually

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General Description
The Samsung M381L3223CTL is 32M bit x 72 Double Data Rate SDRAM highdensity memory modules. The Samsung M381L3223CTL consists of nine CMOS 32M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil) packages mounted on a 184pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The M381L3223CTL is Dual In-line Memory Modules and intended for mounting into 184pin edge connector sockets. Synchronous design allowsprecise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and /CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 2, 2.5 (clock)
Programmable Burst length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
Serial presence detect with EEPROM
PCB : Height 1250 (mil), double sided component
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;) !!


/ShadeK