Popularity of RDRAM products gradually rising

[Kennyshin]

<A HREF="http://www.digitimes.com/NewsShow/Article_print.asp?datePublish=2002/05/29&pages=06&seq=32" target="_new">http://www.digitimes.com/NewsShow/Article_print.asp?datePublish=2002/05/29&pages=06&seq=32</A>

It seems like even PC1066 RDRAM is popular among the Taiwanese motherboard and memory vendors.


<b> Searching for the true, the beautiful, and the eternal </b>

 

[bum_jcrules]

Here is a question for you then...(Not meant to be sarcastic, just the "Devil's Advocate.")

If motherboard manufacturers and vendors are so happy with PC1066 and RDRAM, why don't they have the chipset manufacturers make MCH's that utilize RDRAM for Athlon systems? They could keep the signaling the same from the rest of the northbridge to the MCH. All they would need to do is change the memory controller with its signaling and clock generators and POOF! You have an AMD system using RDRAM.

Now before anyone jumps in and starts telling the world how it could not happen. Think about it and contemplate the question and not the asker of the question. Circuits, chips, and PCB's are all components. Humans are smart enough to get the two working together. So if RDRAM is so fantastic why aren't there chipset using MCH's designed for RDRAM? (Forget the royalties, etc. arguments.)

I just bring this up for discussion reasons. I'm verclempt..."So talk amongst yourselves." The topic is RDRAM and AMD systems.


<b>"Sometimes you can't hear me because I'm talking in parenthesis" - Steven Wright</b> :lol:

 

[Crashman]

You're very silly. To begin with, an Athlon would only require a single channel RDRAM in order to work properly, as in PC1066 has the same bandwidth as PC2100. But the latency would hurt performance on the Athlon.

I think the main reason it is prefered for the P4 is that dual channel operation only requires only half as many signal trances and dual channel DDR SDRAM will, making motherboard design easier.

So basically the P4 requires dual channels for proper performance, while the Athlon does not. Add to the fact that Intel was the majoy push behind RDRAM, causing AMD guys to hate Rambus Inc. even more than Intel guys do.

BTW, most Intel guys dislike Rambus but the smart ones still realize it's the best product avialable at this time for the P4.

What's the frequency, Kenneth?

 

[FatBurger]

Half as many as single-channel DDR, a quarter as many as dual-channel DDR.

<font color=blue>Hi mom!</font color=blue>

 

[Crashman]

OH, yes, you're right of course, RDRAM is only 32 bits per DIMM.

What's the frequency, Kenneth?

 

[bum_jcrules]

I thank you for calling me silly but it comes back to the whole discussion of the memory architectures themselves.

<b>1.</b> What if you put a Texas Instruments 600Mhz DRCG (Direct Rambus Clock Generator) on a motherboard and scaled the memory up to 1200Mhz?

<b>2.</b> Wouldn't the latency penalties be offset by the increased signaling performance?

<b>3.</b> Couldn't you use a RIMM 4200 module?

<A HREF="http://www.rambus.com/company/press/pressreleases/2002/020225a.html" target="_new">"The RIMM 4200 uses the 1066 MHz speed bin of current production RDRAM to deliver the highest performance available to date from a single PC memory module," said Tom Quinn, vice president of Marketing, Samsung Semiconductor, Inc. "A single module that supports two channels of RDRAM with 4.2GB/sec of bandwidth makes RDRAM even more attractive from a price-performance standpoint."</A>

I mean to bring up these points up for the purpose of discussion. The advancement of performance is often done by using current solutions through cross-technological incorporation.

<b>"Sometimes you can't hear me because I'm talking in parenthesis" - Steven Wright</b> :lol:

 

[FatBurger]

RDRAM is 16-bits per <font color=red>R</font color=red>IMM :tongue:

<font color=blue>Hi mom!</font color=blue>

 

[bum_jcrules]

Fatman,

What is your take on this?

<b>"Sometimes you can't hear me because I'm talking in parenthesis" - Steven Wright</b> :lol:

 

[FatBurger]

I don't think that the Athlon needs RDRAM, so pushing it would only needlessly create another confusion in the marketplace (look at all the "Buying a P4 - DDR or RDRAM?" threads").

Latency is still an issue. The P4 needs the bandwidth, and the hardware data prefetch helps hide the latency. The Athlon's data prefetch isn't as good (as shown by the Latency2 results, which was at least good for something), so RDRAM's latency would appear much greater than on the P4.

I don't think that using RDRAM on the Athlon platform is a terrible idea, just one that isn't needed. There aren't really any pros, and a few minor cons.

That said, maybe Hammer will be different? We'll see. The disadvantage being that only one company can choose the memory types (AMD). You can't have Via breaking the rules and bringing out chipsets without permission, or SiS pushing the limits.

<font color=blue>Hi mom!</font color=blue>

 

[Crashman]

A lot of motherboards are already using a 600MHz DRCG. But the problem is...exceeding the badwidth of the system bus with the memory bus provides little to no increase in performance. So RDRAM's high bandwidth would do nothing for the Athlon unless you increased the bus speed of the Athlon significantly. And even at these high speeds, RDRAM has more latency than SDRAM. So any attempt to use RDRAM would A) Not benefit the Athlon with it's higher bandwidth and B) Slow the Athlon with it's higher latency. It's a dead end road.

Dual Channel DDR will most likely be the next big thing for the P4, for those same reasons. The P4 actaully has the bandwidth to support such technology, the Athlon doesn't.

What's the frequency, Kenneth?

 

[Crashman]

Geez, but I thought, uh, never mind :tongue:
Just getting my math mixed up, I knew that Rambus was 8-bit, and that a RIMM had a double wide path at 16-bits, I don't know how I got my math mixed up :frown:

What's the frequency, Kenneth?

 

[bum_jcrules]

That is what I mean. I know that the existing Athlon setup wouldn't be able to take full advantage of RDRAM. How about the Hammers? Incoorporated MCH and a high speed transport system to the main memory. This could use RDRAM or DDR, DDRII, QDR, QDRII, or whatever they decide to use with it.

We still have not come to the conclusion on the latencies issue of the two architectures. And we very well know that using DDR SRAM or QDR SRAM will have lower latencies than DDR SDRAM and should have better bandwidths.

Will the prefetch structures on Hammer(I hate calling it Opteron) and Itanium be better suited by the new memory types or would current DDR and RDRAM be sufficient? Of course the latter but they are only produced as engineering models right now. The prefetches will definatly be enhanced by DDR SRAM's and QDR SRAM's dual clock generators. But would the high speed signalling of PC1066 and PC1200 and the higher bandwidth of the serial architecture be more beneficial from the start and then transition to the JEDEC standards?

"That amongst yourselves..." - Mike Meyers in SNL's Coffee Talk

<b>"Sometimes you can't hear me because I'm talking in parenthesis" - Steven Wright</b> :lol:

 

[FatBurger]

<i>Crashman says:</i>
Just getting my math mixed up, I knew that Rambus was 8-bit, and that a RIMM had a double wide path at 16-bits

Now you're really confused. It's 16-bit, and effective 32-bit because of the dual-channels.

But now that I think about it, you're kind of right. Assuming that you count the double-pump, it could be actual 8-bits wide, or it could be effective 32-bits wide. Not sure...

<i>Bum_JCRules says:</i>
How about the Hammers?

Now that's where it gets interesting. AMD has taken out a license to use RDRAM, most of us know that. But why? They've already said Hammer will use dual-channel DDR, and they're not exactly a big chipset maker, so they were almost certainly never planning on using RDRAM for the Athlon. So are they hedging their bets, or do they have something in store? I suspect they're just hedging their bets and keeping options open, but who knows.

<i>Bum_JCRules says:</i>
This could use RDRAM or DDR, DDRII, QDR, QDRII, or whatever they decide to use with it.

Yeup, but the problem is, even though the MCH is on die, you still have to buy a motherboard with slots to fit the memory you want. So the problem of buying a new motherboard for new memory is still there. <i>Unless</i> we move to hybrid motherboards with slots for DDR, DDRII and RDRAM all at once. However, that would be expensive and impractical.

<i>Bum_JCRules says:</i>
Will the prefetch structures on Hammer

Prefecth will pretty much disappear, to a certain extent. Though it depends on how you look at it, you could say that the MCH disappears and we'll have <i>only</i> data prefetch.

<i>Bum_JCRules says:</i>
and Itanium

I'm not sure how Itanium fits into this?

<font color=blue>Hi mom!</font color=blue>

 

[bum_jcrules]

<i>Fatburger says...</i>
Poster: FatBurger
Subject: Re: Popularity of RDRAM products gradually rising


In reply to:
--------------------------------------------------------------------------------

Crashman says:
Just getting my math mixed up, I knew that Rambus was 8-bit, and that a RIMM had a double wide path at 16-bits



--------------------------------------------------------------------------------


Now you're really confused. It's 16-bit, and effective 32-bit because of the dual-channels.

But now that I think about it, you're kind of right. Assuming that you count the double-pump, it could be actual 8-bits wide, or it could be effective 32-bits wide. Not sure...

Yes, RDRAM is 8 bit using a DDR signal. 2 bit on one wave. So 16 bit. 32 bit because of dual channels.

<i>Fatburgersays</i>:
but the problem is, even though the MCH is on die, you still have to buy a motherboard with slots to fit the memory you want. So the problem of buying a new motherboard for new memory is still there. Unless we move to hybrid motherboards

How will Hammer be designed in terms of a MCH? Is it a programable MCH to interface with whatever memory is at the end of the HyperTransport data path? I thought it was a fixed MCH. Fixed is what I think you mean so multi boards won't work between SDRAM and RDRAM types. Wouldn't they be incompatable?

Could they build a programable MCH? I am sure someone could but that wouldn't be easy if they did. Nor inexpensive.

Data prefetch will of course be there but will there be a main memory prefetch? What if you are on a cluster, wouldn't it need some form of prefetching if the data is on another CPU's memory? Like a 4-way system.

The only reason I bring up Itanium is that it will be in the same boat a Hammer when it arrives. However the MCH will be on the board. But it will still have to deal with the same issues that P4, Athlon, PIII, and every other processor since 8086 has had to deal with.(and maybe even before that)

Back to you...

<b>"Sometimes you can't hear me because I'm talking in parenthesis" - Steven Wright</b> :lol:

 

[FatBurger]

How will Hammer be designed in terms of a MCH?

It is on-die, which obviously creates unusual circumstances.

I thought it was a fixed MCH. Fixed is what I think you mean so multi boards won't work between SDRAM and RDRAM types. Wouldn't they be incompatable?

Yes, so I think that for a multiple memory type board, there would have to be two memory controllers present, and it decides which to use based on which is populated, or by a dipswitch?

Data prefetch will of course be there but will there be a main memory prefetch? What if you are on a cluster, wouldn't it need some form of prefetching if the data is on another CPU's memory? Like a 4-way system.

Prefetch isn't really needed in a sense, because the CPU and the memory controller are (sort of), the same thing. But then it's sort of like it's <i>only</i> data prefetch. I'm not really too clear on how the CPU and MCH will integrate logically.

In a multi CPU system, I would think that each processor would have it's own memory, period. If a processor needs data, it loads it from it's own memory source or the hard drive, never from another CPU. That's pure speculation though. I don't know nearly enough about how it will work (does anyone?), but it's very interesting. Perhaps they'll make it configurable enough so that programmers can choose which CPU/memory processes go to? That could be good or bad.

The only reason I bring up Itanium is that it will be in the same boat a Hammer when it arrives.

I'm still not sure what you mean by that. Itanium is out and about, for one thing. The memory controller is also not onboard (as you said), so I'm still not seeing how it relates to this discussion?

<font color=blue>Hi mom!</font color=blue>

 

[bum_jcrules]

It is on-die, which obviously creates unusual circumstances.

I understand that, however what logical units are the Hammers going to use? I have not found that anywhere so I am in the same boat as you on how they are going to make it work. I just looked at some of the updated stuff and it will have a DDR Memory Controller for Single and Dual Channel DDR interfaces. It will support both Registered and Unbuffered memory. It will support PC1600, PC2100, and PC2700.

Now that seems dumb to me. Why would they limit themselves only to the existing DDR memory speeds?

I know that that is all that exists but does that mean they have to produce new dies for faster and the newer memory technologies? I guess so...

Yes, so I think that for a multiple memory type board, there would have to be two memory controllers present, and it decides which to use based on which is populated, or by a dipswitch?

I doubt a dipswitch. It seems to me that it will be an intelligent controller. If it can differentiate between so many combinations, it must be.

In a multi CPU system, I would think that each processor would have it's own memory, period. If a processor needs data, it loads it from it's own memory source or the hard drive, never from another CPU. That's pure speculation though. I don't know nearly enough about how it will work (does anyone?), but it's very interesting. Perhaps they'll make it configurable enough so that programmers can choose which CPU/memory processes go to? That could be good or bad.

I saw a demo on the information flow. I think it was on their website. I'll look. Each of the processors share the info and can access each others memory. It is displayed in the PDF doc below on starting on page 29.

<A HREF="http://www.amd.com/us-en/assets/content_type/DownloadableAssets/MPF_Hammer_Presentation.PDF" target="_new">All of the CPU's in a cluster can read each other's memory.</A>

It probably can write if it wanted to. I don't see why it would.

If it is looking for data is that a Fetch or a Prefetch? This sis why I think that there would have to be some form of Prefetch.

As for Itanium o'll drop it since I seem to be confusing you...

Back to you all...



<b>"Sometimes you can't hear me because I'm talking in parenthesis" - Steven Wright</b> :lol:

 

[FatBurger]

what logical units are the Hammers going to use?

That I don't know. I only know the general architecture, I don't know much about Hammer logically.

Why would they limit themselves only to the existing DDR memory speeds?

You can't support something that doesn't exist. It's just like motherboards only supporting PC2100, because PC2700 wasn't around then. Doesn't necessarily mean you can't run your memory at 166MHz.

I doubt a dipswitch. It seems to me that it will be an intelligent controller.

Perhaps, that was just an example.

All of the CPU's in a cluster can read each other's memory.

Interesting document, I bookmarked it for future reading.

Looks like that is the case. I would think that would be a pretty difficult to implement, but if anyone can do it, AMD can.

<font color=blue>Hi mom!</font color=blue>

 

[bum_jcrules]

When I said, "What logical units are the Hammers going to use?" I didn't mean for you to answer it because you said you didn't know. I was just wondering about it out loud,

I understand that about existing DDR Memory types, but It would make more sense to have a programable MCH. No?



<b>"Sometimes you can't hear me because I'm talking in parenthesis" - Steven Wright</b> :lol:

 

[FatBurger]

Ah, ok.

Programmable in which way?

<font color=blue>Hi mom!</font color=blue>

 

[labdog]

rofl.


now im a tank, armoured against bs@dum.
<i>if you know you don't know, the way could be more easy

 

[eden]

Modular?

--
Meow

 

[FatBurger]

And by that you mean...

<font color=blue>Hi mom!</font color=blue>

 

[bum_jcrules]

I have been thinking about this...

Why can't someone intigrate a programable logic to the memory controller and the clock generator(s)?

Would it really be that hard? I mean, there are already CLPD, FPGA, and other devices that allow for re-programability for other applications. Why can't someone do it with main memory systems?

I am by no means a degign engineer. Can it be done and has someone ever thought of doing it?

Or am I just crazy...I take that back, don't tell me I'm crazy.

Back to you...

<b>"Sometimes you can't hear me because I'm talking in parenthesis" - Steven Wright</b> :lol:

 

[juin]

, RDRAM has more latency than SDRAM

not sure Pc 1066 have the same latency that DDR 133.Rimm 3200 maybe have less lantency

cheap, cheap. Think cheap, and you'll always be cheap.AMD version of semi conducteur industrie

 

[bum_jcrules]

Fatman and any others that work on PCBs...

What are your thoughts on this?

<b>"Sometimes you can't hear me because I'm talking in parenthesis" - Steven Wright</b> :lol: