Yes the article is confusing. However the fact still remains that the difference between a CAS timing delay of 2 cycles verses 2.5 cycles is miniscule. The differences between what you quoted...
Explanation: the charts show you results that are labeled "Slowest" and "Fastest." The following table shows you the settings we chose:
Fastest Slowest
Act to Precharge 5 7
RAS-to-CAS 2 3
RAS Precharge 2 3
... is an additional 4 cycles. Now take PC2700 that is running at around 166MHz. (500/3 to be exact. I'll use 166MHz for illustrative purposes.) That is 166,000,000 cycles per second. If you add the difference between the Precharge settings (2 cycles), the <b>R</b>ow <b>A</b>ccess <b>S</b>trobe Precharge (2 Cycles), the RAS to CAS delay {1 Cycle) and the <b>C</b>olumn <b>A</b>ccess <b>S</b>trobe (0.5 cycles). The total is 4.5 cycles. That difference is 4.5 cycles out of the 166,000,000 cycles per second. That is one tiny, tiny, really, really, really, small number. (4.5 cycles /166,000,000 cycles per second = 0.0000000271 seconds. If I used 166,666,666.6667 that number would be even smaller. 0.0000000270 seconds. <font color=red><b>That is about 3 tenths, ...of a millionth, ...of one second</b></font color=red>. hehe)
So you can see, that the difference in the timing of your memory will not be that significant. Using faster memory would be a better improvement than better timing settings on the same memory.
Back to you...
<b>"Sometimes you can't hear me because I'm talking in parenthesis" - Steven Wright</b> :lol:
EDIT:
It seems to me that a lot of people here get their panties in a knot about this issue. The most aggressive timing setting don't matter as much when the clock speeds are so fast. Back in the day of Fast Page, EDO, Burst EDO, or even PC66 those timing settings had more meaning. However with DDR there ate two bits per cycle and the speeds are faster. So to say it clearly, Timing between CL2 and CL2.5 doesn't really matter!!!