Crucial CAS 2.5 to CAS 2

[Oracle]

Anybody ever had any experience running a Crucial PC2100 CAS 2.5 module at CAS 2 stable?

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[Rainchill]

I've run it that way for a year now, no problems what so ever. I've seen reports claiming it can go as high as 166 mhz cas 2.0.

 

[bum_jcrules]

For SDRAM, the higher the speed the lower the CL, CAS latency, setting you can use. At core speeds of 100MHz a CAS 2 setting should be viable. (Junk brands might not allow for this. Quality is the other key to lower latency settings.) You are using Crucial. With that kind of quality you should not worry about a CL setting of 2.0.


(I posted this on another thread, but it is worth repeating.)


In addition...

I thought that I should add this for those of you who wonder if your memory can handle a CAS Latency 2 setting.

tCLK = System Clock Speed

CL = The CAS Latency

tCAC = Column Access Time

<A HREF="http://www.vml.co.uk/Support/Sdram Timing.htm" target="_new">The "rule" for determining CAS Latency timing is based on this equation: CL * tCLK >= tCAC

In English: "CAS Latency times the system clock cycle length must be greater than or equal to the column access time". In other words, if tCLK is 10ns (100 MHz system clock) and tCAC is 20ns, the CL can be 2. But if tCAC is 25ns, then CL must be 3. The SDRAM spec only allows for CAS Latency values of 1, 2 or 3.</A>

This is based off of 100MHz PC100. So for PC2700 which is a 166.667MHz clock and the fact that most DDR is a CAS 2.5 clock cycles. So the switch is only 0.5 cycles to CAS 2.

So... on a 266 FSB / 133.33MHz x 2 or 400/5 system clock... the tCLK should be around 7.5ns, nanoseconds. (1 second = 1,000,000 ns)

<b>1 second / 1 MHz or cycles per second (clock speed) = 1000ns</b>

(1 MHz = 1,000,000 cycles per 1 second.)

So for 400/3Mhz or 133.33MHz the tCLK will be...

<b>1000ns /(400/3) = 7.5ns</b>

<b>CL * tCLK >= tCAC</b>

<b>2 x 7.5 = 14ns</b>

So for a CAS latency setting of 1.4 would be enough. So you should be more than able to run PC2700 in this example at CL2.

<b>"If I melt dry ice in a bathtub, can I take a bath without getting wet?" - Steven Wright</b>

 

[Oracle]

Thanks for your posts fellas!
Bum, I wasn't expecting such a comprehensive explanation! Thanks
So, according to this, I could run my modules at CL1.5 if that setting was available, right?

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[Oracle]

CL2 @ 166Mhz!!!
Wouldn't that be pushing the envelope a little too much?
According to Bum's calculations here, there should be problems running such specs.


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[bum_jcrules]

Yes.

As for you statement...

"CL2 @ 166Mhz!!!
Wouldn't that be pushing the envelope a little too much?
According to Bum's calculations here, there should be problems running such specs."

As the clock speeds increase, the lower the latency settings need to be.


BTW: Does anyone remember Tom talking about CL settings at 1.5? This is why he was talking about it.



<b>"If I melt dry ice in a bathtub, can I take a bath without getting wet?" - Steven Wright</b>

 

[Oracle]

I agree.
But is there any BIOS that would let you adjust a CL lower than 2?
I don't know, I'm just asking?


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[bum_jcrules]

Even if there was, it won't improve your system much. From CL 2.5 to 2 on DDR systems the time improvement, at 500/3MHz (or 166.667), is only 0.0000000270 seconds. So for a one half clock from 2.0 to 1.5 it is the same improvement.

That is about 3 tenths, ...of a millionth, ...of one second.

That is not worth the hassle to set the CAS Latency at 1.5 cycles. Speed increases are much better overall. So until FSB clock speed increase we will have to take these miniscule improvements through lover latencies.

If you look at the number of bits that are delayed for 0.5 cycles on DDR is only 1 bit.

0.5 cycles x 2 bits per cycle = 1 bit.

Now that is 1 bit per second. The difference of increasing the speed by 0.5 MHz is 1,000,000 bits.

So you can see that speed is more important that latency settings. I am not saying that lower latencies are not important at all, just not <b>AS</b> important as increased clock speeds.

<b>"If I melt dry ice in a bathtub, can I take a bath without getting wet?" - Steven Wright</b>

 

[Oracle]

So I guess now that 400Mhz DDR-SDRAM can be had, the next big step for AMD and chipset manufacturers would be to increase FSB, wouldn't it?
(Avoiding Intel on purpose not because I'm a AMD fanboy but because their bus has already reached 400Mhz)
Pentium 4 finally found its match.
What's Hammer supposed to run at?


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