about DDR

[foresnow]

I want to know the exact function of DM(data mask) pin in DDR SDRAM.
This pin is only used in write to precharge period or write to read period,but ,why it begain to mask input data several clock cycles before the precharge or read command,not just at the clock positive edge of precharge or read ,what the system or the SDRAM will do during these several clock cycles?
Thank you !!
foresnow

 

[10GHZ]

i have no idea, but maybe u can find what u want if u do a google serach, or maybe anyone else?

 

[bum_jcrules]

Good question...

I see that too. It is Pin 47 on x4 (DM), x8 (DM), and x16 (UDM). x16 has an additional one on Pin 20(LDM).

The <i>Micron DDR Preliminary White Sheets</i> have it stated this way on page 7.

"Input Data Mask: DM is an input mask signal for write data. Input 20, 47 LDM, UDM data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. For the x16 , LDM is DM for DQ0-DQ7 and UDM is DM for DQ8-DQ15. Pin 20 is a NC on x4 and x8."

To quote again from page 2...

"The double data rate architecture is essentually a 2ns-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins."

You can read on if you like...

Basically...

When a write is taking place there is a sampling taking place. So if the results come back "High," the data is then masked. (What does "High" mean....??? I don't know.)

So if you are looking for something more concrete than that... I might not be able to help. I can only tell you what I know or what I read.

<b>"If I melt dry ice in a bathtub, can I take a bath without getting wet?" - Steven Wright</b>

 

[foresnow]

Thank you !
I have read the DDR specification ,but...I can not understand it really.And, there is a functional block diagram in page 5,it is too complex for me.