Dual Channel DDR basic question

[jlanka]

Here's a basic one:

Will Dual Channel DDR chipsets require special DDR at all? Or whatever is on the market right now will work fine, as long as it's clockable up to whatever speed the new sets will come in at?

Thanks in advance.

<i>It's always the one thing you never suspected.</i>

 

[bum_jcrules]

No. DDR is SDRAM so it is parallel. You do not need anything special for a dual channel board.

BTW/PSA: With an AMD system... A dual channel board will not yield superb results over a single channel board. The reason is the FSB. No matter how much memory bandwith you have it still has to pass from the memory controller across the FSB to the CPU. So the FSB limits the available information that the memory bus can supply. On a P4 system it is a different story. It has a wide FSB and normally it is a 1:1 ratio between the size of the FSB and the memory bus. An AMD using DDR333 will have a memory peak bandwidth of ~2.667GB/s. However the FSB is only 2.133GB/s. So the effective bandwidth is the least common denominator, aka, the 2.133GB/s of the FSB.

<b>"If I melt dry ice in a bathtub, can I take a bath without getting wet?" - Steven Wright</b>

 

[eden]

But there would still be a data burst, which can still increase slightly the performance, no?

--
The sound of determination is the echo of will...

 

[bum_jcrules]

Yes.

Answer this...This is not ment to be 100% sarcastic, maybe 99%. No...I want to ask you these questions to make you think or to do some research.

1. Is it going to be using burst all the time?

2. When you do what bandwidth is it going to be constricted at?

I'll wait for the reply...

<b>"If I melt dry ice in a bathtub, can I take a bath without getting wet?" - Steven Wright</b>

 

[Crashman]

The SiS 655 will come out using standard DDR DIMMs for the P4, offering superior performance to any DDR board yet produced for the P4, unless they seriously screw up the design.

<font color=blue>By now you're probably wishing you had ask more questions first!</font color=blue>

 

[bum_jcrules]

Well it has been 7 hours...

Let me define the terms and show some applications.

Burst Mode:
A high-speed transmission mode in a communications or computer channel. Under certain conditions, the system sends a burst of data at higher speed for a limited amount of time. For example, a multiplexor channel may suspend transmitting several streams of data and send one high-speed transmission using the entire bandwidth.

1. So since it is only for "limited amount of time," you will not use it all the time.


For the second lets look at the old Burst EDO memory type for our answer of which bandwidth is bursted.

BEDO (Burst EDO) is a faster type of EDO that gains speed by using an address counter for next addresses and a pipeline stage that overlaps operations.

2. There are two ways to burst data. One is using the memory bandwidth because it uses memory controller and the memory clock generator to burst the data. Using multiple commands at once while using a counter to know exactly when to send the packet of info. There is a higher latency involved with bursting in this fashion. The timing has to be correct or there will be complications in addressing which wastes a lot more clock cycles than it saves.

The other idea of bursting is where there are smaller transmissions that are then clumped together into one larger packet. However this is not efficient for memory which is already taxed. Why should it send smaller packets when it can send lots of large ones in the same amount of time? This isn't really used in memory, more in network and internet applications.

Sorry for the long explanation.

The answer to the second is that it will be the memory bus that is bursted and will still be constricted to the maximum bandwidth of the FSB. Even if the FSB was bursted, it would still be confined to the 64bit x 2 channels x 133MHz (non OC'ed) = 2.133GB/s.

<b>"If I melt dry ice in a bathtub, can I take a bath without getting wet?" - Steven Wright</b>