Eden,
Sorry I went on ahead. Let me come back to the DDRII standard. The DRAM memory types will be the form FPBGA, higher clock speeds, and lower voltages. That is all DDRII really is.
DDR as you know is Double Data Rate.
QDR is Quad Data Rate.
QDR is 4 bits per signal cycle where DDR is 2 per signal cycle.
However: The next round of memory parallel types will take the form of DDRII (SDRAM, FCDRAM, RLDRAM), DDRII VCSDRAM, DDRII SRAM, QDR SRAM, and QDRII SRAM.
The latter three are the lowest latency forms of parallel memory types.(To date.) DDR SRAMs and QDR SRAMs are in production and the others are in engineering forms. However the production of the others are slated for this quarter.
I bring up the SRAM side because this is being shipped to end user product manufacturers.
Network applications, video applications, etc. With 36Gb/s of bandwidth imagine the improvements that can take place. This is only the surface.
Juin,
You are correct. I should have posted <A HREF="http://www.samsungusa.com/cgi-bin/nabc/semiconductors/search/datasheet.jsp?family=554" target="_new">this for you</A>. However those are only showing engineering samples available in November. Also that is only Samsung.
Either way..."Where are you getting your numbers from?"
Why would the latency settings increase?
Everything out there points to lower latencies, lower voltages, smaller packaging, and higher speeds as the next round of technology comes out.
I mean even Micron and Infineon are building low latency versions of DDRI and DDRII. It is called ELDRAM.(Reduced Latency DRAM) Get the <A HREF="http://www.rldram.com/datasheets/index.html" target="_new">data sheets here</A>. Toshiba and Fujitsu call it FCRAM.(Fast Cycle DRAM) Get the <A HREF="http://www.fme.fujitsu.com/products/fcram_new/consumer.html" target="_new">sheets here from Toshiba</A> or read <A HREF="http://www.toshiba.com/taec/components/Generic/WP_memory.shtml" target="_new">this to understand what they are doing by looking here</A>. If memory makers use the SRAM column registers for <A HREF="http://www.lostcircuits.com/memory/eddr/" target="_new">EDDR DRAM</A> and EDDRII DRAM, that means that a CAS latency of zero cycles. (CL0) The memory will have the row strobe and the column will have its info static, a.k.a. No latency penalty.
So why would you state 5-5-5. Which settings are those anyway?
SDRAM Idle Limit: 0, 8, 12, 16, 24, 32, 48 cycles
tRC Timing: 3, 4, 5, 6, 7, 8, 9 cycles
tRP Timing: 3, 2, 1, 4 cycles
tRAS Timing: 2, 3, 4, 5, 6, 7, 8, 9 cycles
CAS Latency: 2.5, 3 cycles
tRCD Timing: 1, 2, 3, 4 cycles
Only two have settings for 5 cycles...tRAS and tRC.("tRAS" the minimum page open time and "tRC" the bank cycle time.) And as I posted above there are a lot of improvements already started and some are scheduled for mass production this quarter.
<b>"If I melt dry ice in a bathtub, can I take a bath without getting wet?" - Steven Wright</b>