Ok, I am building a new computer very soon. I am going to be running a p4 2.53ghz and an intel D845PEBT2 motherboard. Clearly I will not be overclocking due to the mb i will have but maximum performance IS something I am interested in. Now, I am going to go with 512megs of memory. I have all along been planning on just getting some Corsair XMS pc-2700 so I can run it at CL2... but now googlegear has a 512 stick of Kingston or Samsung for only $140... Does anyone know if you can run the Kingston/Samsung sticks at CL2??? they aren't specced to do so but I have heard that sometimes it works ok. Please let me know, it's important to me.
"There is no dark or light side, only power and those too weak to seek it."<P ID="edit"><FONT SIZE=-1><EM>Edited by vegandago on 11/28/02 12:05 PM.</EM></FONT></P>
SO to answer what CAS Latency you want. 2.5 vs. 2 does not really make a difference. You are talking about one half of one clcock cycle.
So let me do the math for you.
DDR333 = PC2700 = 166.6667 or 500/3 MHz with a DDR signal
Okay, so 0.5 cycles divided 500,000,000/3 cycle per second = .000000003 seconds.
Not much difference there. It equates to a max of 1-3% performace gain. Probably only a 1%. The faster the memory the smaller the gain by latency timings. Speed is much more significant than CAS latency settings. Even if the CAS Latency (CL) was .5 (Instead of 2.5) that would still only be 0.000000012 seconds better.
Agreed. CL is as the name implies LATENCY. That means when you read (and CL only affects reading) your data takes 1/2 clockcycle longer to arrive. It doesn't mean that that 1/2 clockcycle is wasted, since memory accesses are pipeline. So in theory CL doesn't affect bandwidth at all.
But depending on the memory controller a bit is wasted now and then and hence bandwidth is a few percent higher with CL2.
In some extreeme case CL can have a huge impact. Consider a situation with a lot of single word accesses to memory. further, you need the result of one access before you can start the next. In that case the accesses can't be pipeline and the 1/2 clockcycle is wasted. Further 1/2 clockcycle wasted compare to a single word access is a huge percentage. However, this is a constructed situation and extremely rare in reality.
Do you expect a long FAQ with all kinds of timing settings? Otherwise, It should be added to the memory FAQ. Fatburger is kind of busy at the moment, but if we figure out a short and concise way of explaining this, Im sure he will add it the memory FAQ.
I quess we could put something under Fatty's FAQ but I still think that there needs to be a place for people to learn about how memory works, what the timings are for, and what they can do to tweak their machines.
I don't know of any one place on the net that does that. I have links to places all over the net but that won't people and their own learning curves.
So if we could come up with something to first create a flow chart of operations. (General of course.) Then explain SDRAM, DDRSDRAM, and RDRAM. Then go into detail of the structural differences of the three main types. The timing differences.
Once people know how RAM actually works, how it interacts with the FSB and CPU, and what impact timing settings, signalling, and speed have on memory itself.
I know this is more of a job for THG itself to do in building a memory section on the main site, but until that is built, if it ever is, I would rather inform the community here and bring them all up to speed on memory technologies.
So what do you think, are you up for something like this? It would be a project.
I don't know how much I will contribute for now. My daughter was just born last week and I only have three weeks for this LAN. So after that I will be able to devote more of my time to it.