I bought 2 modules of Infineon Ram, 2 x 512 MB DDR 266. I find it cheap, but I doubt it's not Infineon RAM because on two modules no logo or sign of the brand. Shopkeeper said he finished labels to stick on them, directly from Infineon.
I have another DDR 512 module, no brand, installed before these new two. I tried to test these modules with Sandra Standard, no excellent results compared to my system configuration, with CpuId PCWizard, no results for memory benchmark, then with Cpu-Z where I know these information about Ram (the same of PCWizard):
Hi. From the infenion site. Sorry it's formatted with windows notepad. Just replaced my hard drive and been to lazy to install word.
512-MBit Double Data Rata SDRAM
Preliminary Datasheet 2002-03-17
Page 1 of 77
• Double data rate architecture: two data transfers
per clock cycle
• Bidirectional data strobe (DQS) is transmitted
and received with data, to be used in capturing
data at the receiver
• DQS is edge-aligned with data for reads and is
center-aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK
• Commands entered on each positive CK edge;
data and data mask referenced to both edges of
• Burst Lengths: 2, 4, or 8
• CAS Latency: (1.5), 2, 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8µs Maximum Average Periodic Refresh
• 2.5V (SSTL_2 compatible) I/O
• VDDQ = 2.5V ± 0.2V
• VDD = 2.5V ± 0.2V
• TSOP66 package
The 512Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing 536,870,912
bits. It is internally configured as a quad-bank DRAM.
The 512Mb DDR SDRAM uses a double-data-rate architecture
to achieve high-speed operation. The double data
rate architecture is essentially a 2nprefetch architecture
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access
for the 512Mb DDR SDRAM effectively consists of a single
2n-bit wide, one clock cycle data transfer at the internal
DRAM core and two corresponding n-bit wide, onehalf-
clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver.
DQS is a strobe transmitted by the DDR SDRAM during
Reads and by the memory controller during Writes. DQS
is edge-aligned with data for Reads and center-aligned
with data for Writes.
The 512Mb DDR SDRAM operates from a differential
clock (CK and CK; the crossing of CK going HIGH and CK
going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read
orWrite command. The address bits registered coincident
with the Active command are used to select the bank and
row to be accessed. The address bits registered coincident
with the Read or Write command are used to select
the bank and the starting column location for the burst
The DDR SDRAM provides for programmable Read or
Write burst lengths of 2, 4 or 8 locations. An Auto Precharge
function may be enabled to provide a self-timed
row precharge that is initiated at the end of the burst
As with standard SDRAMs, the pipelined, multibank architecture
of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row
precharge and activation time.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2,
Class II compatible.
Note: The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled
mode of operation.
CAS Latency and Frequency
Maximum Operating Frequency (MHz)
2 100 133 133
2.5 125 143 166
512-Mbit Double Data Rate SDRAM
Page 2 of 77 2002-03-03
Pin Configuration TSOP66