XDR DRAM aka Yellowstone

[bum_jcrules]

Someone else tell me if I have this down wrong. I keep looking at the specs for XDR and it looks like they are going to have dual channel in each chip.

400MHz x 2 Bytes (16 bit) x 2 bits per clock (DDR signal) x 2 connections per chip = 3.2GB/s

Now they say that with the interconnects it would be 6.4GB/s.

Now I would hardly call that a real ODR signal.

What are your thoughts?



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[Guest]

Here's an intersting piece of article I found

Warmke said XDR DRAM uses a 400 MHz clock but achieves 3.2Gbits/s data rates by using octal data rate (ODR) signaling, transmitting eight bits per clock cycle. As clock rates approach 800 MHz in the near future, ODR will bring a corresponding increase to 6.4Gbits/s, he said.

So from that quote I think the 6.4gb/s wil be reached by increasing the frequency.
Imma keep readin some on that hw.

 

[Guest]

Something to keep in mind is octal data rate is a requirement on information transferred per clock cycle. It is not necessarily indicative of a bandwidth until a clock rate, and buswidth is specified. You have already assumed a a value for these in your formulas.

Maybe these are details that are from the datasheet. I wouldn't know I haven't seen it. Do you have a link?