Warmke said XDR DRAM uses a 400 MHz clock but achieves 3.2Gbits/s data rates by using octal data rate (ODR) signaling, transmitting eight bits per clock cycle. As clock rates approach 800 MHz in the near future, ODR will bring a corresponding increase to 6.4Gbits/s, he said.
So from that quote I think the 6.4gb/s wil be reached by increasing the frequency.
Imma keep readin some on that hw.
Something to keep in mind is octal data rate is a requirement on information transferred per clock cycle. It is not necessarily indicative of a bandwidth until a clock rate, and buswidth is specified. You have already assumed a a value for these in your formulas.
Maybe these are details that are from the datasheet. I wouldn't know I haven't seen it. Do you have a link?