Here's the best explanation I've found. DDR400 RAM has an 8-byte bus. So... transferring 8 bytes at 400mhz = (8 X 400) = 3200 MB/S. On an AMD system, where the FSB is 400MHZ and 8 bytes, this means the processor and RAM have parity, as fast as the processor asks for information, the RAM supplies it. Now, we get into Intel procs, which run at an 800MHZ FSB. The Intel processor has an 8 byte bus width, so is requesting information at (8 X 800) = 6400 MB/S. So our same DDR400 can only satisfy half that requirement. What designers did then was basically make it so the motherboard could act like it had 2 seperate banks of RAM. So you run your 512 in dual channel. Now the processor sees these 2 seperate channels as one, big, fatty channel that is 16 bytes wide(kind of like using 2 water hoses to fill up a pool, the hoses actually put out the same amount of water, but to the pool, it's like one big hose). So now, our DDR RAM transfers data at (16 X 400) = 6400 MB/S, and once again has parity with the processor. This was also implemented in AMD (not the exact same way), but if you see above, it's not much better because the single-channel RAM could already supply data as fast as the AMD processor needed it.
"It's too late now anyway. That song is stuck in my head and the only way to get rid of it is to blow it out. With a bullet!! - Carl