Question about mem controllers

Hi all =) In my research for building my next computer, one of the things I've been reading about is the difference in memory handling between the two manufacturers. So if I have it right, Athlons have the memory controller on-chip, and Pentiums are handled on the motherboard? What I was wondering is how the FSB is determined... Is there a physical limitation imposed on bandwidth by the motherboard architecture that limits the FSB to 200? Also, is it a function of both the chip and the controller or just the controller itself? For example, in the case of the Athlons if you want to change the FSB you obviously need a new CPU just because the controller happens to be built on the chip. On Pentiums, where the memory controller isn't integrated, is changing the FSB a matter of changing the motherboard where the controller resides, or do they need to redesign the chip as well?

Intel is going to the 1066 FSB on its next release of high-end chips. The next P4 "Extreme" is 3.73Ghz and 1066. I assume at some point the mainstream chips will follow suit and go from 800 to 1066. From this it seems like there is something in the chip that determines FSB. But in the overclocker's forums, the P4 guys routinely make huge changes in FSB that seem to make use of more of the bandwidth available on this DDR2 stuff. A lot of DDR2 memory is already rated above PC 3200. There is PC2-5300/667 and they're already speccing out DDR2-800 stuff from what I've been reading. I guess I'm just wondering why, because unless there is something else to the story, this stuff won't be standard for a long, long time.
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More about question controllers
  1. On A64's you raise the memory bus and CPU synchronously (overclocking). On P4's you raise the memory bus and CPU simultaniously (overclocking) and the chipset has ratios available (the best being 1:1). Faster than standard memory is for overclocking.

    The thing that limits bus speed on P4's is the chipset. Newer chipsets tolerate higher frequencies. Different speeds are supported up to the stability limit of the chipset.

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  2. What limits bus speed for Athlons?
  3. Quote:
    What limits bus speed for Athlons?

    The board, most Athlons boards will let you set the RAM bus and the CPU bus at different speeds, however, just like Crashman said above, 1:1 is the optimal setting.

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  4. From what I understand FSB and BUS SPEED are usually not the same thing. FSB is essentially a property of your processor; BUS SPEED is the frequency of data on the physical bus between your processor and memory controller.

    Since for AMD, the memory controller resides on the processor, there is essentially no delay between your memory modules and processor.

    With Intel chipsets, there is a big possibility of delay between processor and your memory modules because in many cases your memory bus and FSB are not sending data at the same rate.

    In any case, the relationship between FSB and BUS SPEED is as follows:

    BUS SPEED = FSB x (sampling rate)

    where sampling rate is x1 for synchronous bus, x2 for double-pumped bus, and x4 for quad-pumped bus.

    For example, its possible to overclock a P4 processor to FSB 266. On a quad-pumped bus this equates to a bus speed of 1066MHz.

    The ASUS P5AD2 Deluxe can be overclocked to 280FSB, which is equivalent to bus speed of 1120MHz (QPB) !! (Here's some real support for DDRII)
  5. That makes sense, thanks =) So the Bus Speed of the chip is something that can't be changed. Then you have to wonder why Intel didn't go to an integrated solution. Seems to me the only advantage of not having the memory controller on the chip would be if you could change aspects of the data rate between the CPU and memory controller "on the fly". Then again, if it wasn't cost prohibitive you might even be able to do something like that with an on-chip controller. But just a guess that that kind of tech doesn't exist yet and probably won't as long as the the companies keep piddling around with clock rates and L2 cache size.
  6. Quote:
    as long as the the companies keep piddling around with clock rates and L2 cache size.

    Well, that is what sells the majority of their chips, not performance. :smile:

    Something seems backwards about this? Perhaps its just me.

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