1. Is a side of a memory module only considered a rank if it has memory chips on it? That's how I interpret/read your response and the info I got from AMD.
Single rank modules have chips on one side. Many PCBs do not support the soldering of chips on two sides. Thus the PCB can be designed differently with this in mind.
2. Do the most common memory configs have one logical bank to each physical rank? Is that the most efficient config or is it more efficient to split the banks onto different ranks?
Normally 1 rank = 1 bank. So that is why people often confuse RANK/BANK. The wiring of most PCBs is designed for 8 chips per rank. And in this case, the 8 chip rank equals 1 BANK.
It is common for chips to be x8 or x16 bits wide, either 32M or 64M in depth. The logical partition for any binary system follows base 2 values. And so a PCB can have 1, 2, 4, 8, or 16 slots for chips etc...
8 chip-slots seems to be a good number for the PCB. There are some older PCBs with slots for 16 chips per RANK. And notebook PCBs are designed for 4 chip-slots per RANK.
Of course memory chips can be made smaller, so can the PCBs. And certainly they are for some technologies like cell phones, PDA, hand held electronics etc.
The trouble is, once a technology gains momentum, that momentum dictates future technologies as well, because it is too expensive to make changes in the middle (take a look at how expensive DDR2 is for example). For DDR memory modules, they are still taking form factors that were used in early SDRAM systems; because the standards are in place and easy to follow.
If your design calls for a 128-bit data bus, where the module has to be single sided, then you will end up with 1 rank, 2 banks, where each bank is organized into a single 64-bit data bus. This is not common, but it can be done.
For dual-channel configurations, the channels are divided necessarily by BANK, but not necessarily by RANK.
note:
It is possible to run a single-sided module in dual-channel if the RANK is divided into 2 BANKs. You just need a 128-bit channel per rank, 64-bit channel per bank. And also you need a chipset that will recogize the logical partition of BANKS.
example:
***PCB DESIGN***
-9 sockets total. No soldering on the opposite side
-BANK0 = slots 0 - 3
-BANK1 = slots 5 - 8
-slot4 is for the ECC chip.
***CHIP CONFIGURATION***
-8 chips total: (64Mx16) each
***BANK CONFIGURATION***
-4 chips per bank.
- 64M depth
- x16 data bus
-COMBINED = x16 x 8 chips = 64-bit data bus
***MODULE SPECIFICATION***
-Two banks each 64-bits wide
-Total memory size: 2GB.
Is this module configuration being mas-produced: no
Is it possible to build: yes
Theoretically, the configuration that offers the best performance would be a very wide memory bus with a shallow memory delth. 1Mx32 for example would have a high performance value. But since 1Mx32 has a particularly high real-estate value, it is not a cost effective design. And so the standards are set for cost/performance in mind.
The analogy would be between:
1. A very tall building with many floors
vs.
2. A large area one story building with many rooms.
Where the performance is a measure of how fast people can get to their desk. Of course it's quicker in the one-story building, but as you know it's much cheaper to build up. Same is true for electronic components.
3. What's the easiest way to determine if a memory module is SS or DS?
Look at chips on the PCB. If there are chips on both sides of the PCB you can be certain it's DS. Chips on one side is a SS module.
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<font color=red>AIM BrentUnitedMem