So power consumption has gone up 18-fold and die size has gone up 15-fold and performance has been dropping off all the time in respect to past counterparts as in if past CPU's were running higher MHz they'd be faster...thats FSB and clock speed......
Well.....i486 Dx-2 66Mhz......look at its FSB...similar to clock speed no?? LoL
Since most integer (excluding multiply/divide) and address generation instructions are already at the below 3 tick count 486+, many being already at 1, instruction parallelism has reached its theoretical maxim. Assuming you can achieve the holy grail of 2.5 instructions per clock. You only have an allowance for 2x to 4x improvement. It's like this. How many times can you run around your house with your underwear on your head before you're little brother or sister can?
(Edit: removed "/transcendental" habit for listing excluded group of instructions based on tick count. There are no transcendental instructions in integer.)
I could say the same for an Athlon ALU, it's not overly different from the P4's besides not being double pumped. Even with that, there are tons of IPC increases elsewhere to be found that make the P4 superior to the 486. I don't recall when was it that the best IPC increases are in tweaking the execution stages. It often is in the cache, the decoding, the branch predicting and prefetching to make sure the data bus is fully utilized.
You're still wrong to claim IPC is the same.
This post is brought to you by Eden, on a Via Eden, in the garden of Eden. :smile: <P ID="edit"><FONT SIZE=-1><EM>Edited by Eden on 01/15/03 04:06 PM.</EM></FONT></P>
You know, it's nice to see someone trying to make an informative claim and then have people mock him with completely irrelevant information. DiVX is almost purely FPU based and its performance has nothing to do with comparing the integer component of a 486 to a P4.
That said, looking at the design of the P4 compared to a non-pipelined, non-superscalar processor like the 486 and I begin to wonder why Intel would claim such a thing. It's true that for non-repeatable code, the P4 would most likely reach the same throughput per clock (maybe even less) than a 486 provided there aren't any limitations with cache/memory. However, since the majority of code is repeatable, the P4's superscalar design should help it gain quite an advantage over a 486 even per clock.
"We are Microsoft, resistance is futile." - Bill Gates, 2015.
You know, it's nice to see someone trying to make an informative claim and then have people mock him with completely irrelevant information.
I'm sorry but in the end all this is just a smoke and mirrors or appeal to tradition fallacy. If the graphs and data had some true information behind it, there would be a reason for a true discussion and they wouldn't have that disclaimer at the bottom I mentioned. It works like this. Look at the birdie (instructions per clock) see the blimp (megahertz), blimps are big, and birds are small. IPC doesn't matter. If juin would back up some of his random statements and quotes, he wouldn't get so much flack.