Is it a legal issue? Will they support it in the future?

The Athlon 64 has SSE2 support but the new P4 Prescott CPU will have SSE3!

No legal issues. In fact, Intel <i>wants</i> AMD to support it so that software developers have no reason <i>not</i> to implement it.

Perhaps that's why AMD has taken so long to put it in: They want to give Intel a hard time... Just conjecture. Anywho, AMD's Hammers have it.


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They need time to design it. Things aren't designed overnight you know. While Intel has months or perhaps even years ahead of time to design an SSE2 implementation before they release SSE2 specs, AMD only has until Intel officially releases SSE2 specs before they can even start designing their own implementation. Adding SIMD capable hardware and an ISA extension isn't exactly like slapping a sticker on a box you know. It requires a significant core redesign and only when Intel is done and releases the specs can AMD even know what to start designing for. Hammer will have SSE2 built-in and when Prescott comes out, SSE3 specs will be released and AMD can start designing an SSE3 implementation.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

Nothing say that PNI is a vector base ISA.I dont say that is not a vector instruction set but that can be something else.

Just next to the lab and the bunker you will find the marketing departement.

It seemed to me Palomino's SSE was not overly hard to implement, nor did it take a long time to properly implement.

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Consider the time difference between the P3 Katmai's release and the Palomino's release.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

Perhaps, but I don't think AMD was even considering SSE at that time, being so faithful to 3dNOW. At the time, it had some boosts in games like Quake 2, so AMD had no intent to consider the competitor's extensions. I'd say they began thinking when they reached 0.18m, if not at 1GHZ.

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To give a idea 2005 CPU are allready in developement

Just next to the lab and the bunker you will find the marketing departement.

Well, certainly at AMD things aren't designed overnight.

Seriously though, I'd hardly consider <i>years</i> to be 'overnight'. If it takes AMD <i>that</i> long to design something as simple as SSE2 support <i>when they already have the APIs</i>, then it's no wonder that they're having problems lately.

I mean at least half of the time Intel spends on designing things like SSE2 is on the programming interface, not on the hardware. Once you have the concepts in mind and the accessing/interfacing methodology figured out, the hardware part just falls into place. Sure, it takes time to design the hardware and even more time to work out all of the bugs, but that's hardly even half of the time it takes to develop it overall. And all that AMD has to do is the hardware part. So it <i>should</i> be easy compared to what Intel put into it.

Don't you find that kind of sad, that AMD takes <i>that</i> long to implement something that we all <i>know</i> will help boost their performance?


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I have to fully agree with you Eden. In fact, I'd take it one step further.

When the P4 first came out, everyone laughed at how it practically relied upon SSE2 just to make up for Willy's design flaws. AND fanboys had field days with Intel believers, saying how almost <i>no</i> software had SSE2 support and so for 'real' applications, AMD kicked Intel's arse.

I think AMD itself was part of that mentality. I think the folks at AMD <i>purposefully</i> avoided giving any support to SSE2 for as long as they possibly could <i>just</i> so that SSE2-optimized apps would be few and far between.

Only now, they're not. It's a pretty common thing and easy to do with an Intel compiler. SSE2 has most definately caught on. And so, AMD finally releases (or at least will soon release) a core with it in.

I don't think that it had anything to do with taking time to implement. I think that it had everything to do with AMD wanting to give software developers as little reason as possible to optimize for SSE and later SSE2 because AMD believed that 3DNOW was better and especially when it came to SSE2, so long as software wasn't optimized for SSE2 the Athlon stood up very well against a P4.


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Exactly my point and also why I think as well, that it is silly they took all this time for SSE2 implementation. Barton could've implemented that instead of the extra 256K L2, take much less space, let alone power consumption, AND would've beat the P4 in almost everything that got it this far.
Again as I said before, just why are the company managers lately so damn unsynchronized with the public opinion and consumer needs.
Same with nVidia, same with AMD.

Do they even have marketting departments lately? OR, is production itself put for the marketting dept.?
Oy, I am getting lost asking questions I can't phrase properly anymore. Guess my point is just that, monkeys confusingly running companies.

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Personally I think AMD is hanging on a thread with the Athlon. They have pushed the Athlon core to the absolute limit and squeezing every last drop of performance out of it...and its running out of juice fast !

I think one of the main reasons AMD ditched the Q2 release date for Athlon64 was because of low yields and the high price of SOI on a mass scale.

I will like to see some benchmarks on how the Opteron handles SSE2 when it is released at the end of April that way we will get a clearer picture to how well 'Hammer' deals with SSE2 optimisations. Will we see more/less/same performance leap in optimised / non-optimised software in comparision to the P4 ?!

<A HREF="http://www.theinquirer.net/?article=7765" target="_new">Waiting for Opteron SSE2 benchmarks.</A>

<font color=purple>Ladies and Gentlemen, its...Hammer Time !</font color=purple>

I don't think I can agree. The API is <b>not</b> that huge a deal. I mean, honestly, you just need the instruction set. Add instructions, subtract, multiply, divide, shifting and rotating instructions and have each of them for all the different data types.
How to carry those instructions out, the decoding of the instructions, register operations, figuring out how to carry out a vector operations without dedicated vector math units, scheduling, alignment, reordering and repacking of the resulting data, and all the transistor design that comes with it. That is not "simple". I don't know why people think SSE is like slapping extra cache on, it's not. Adding additional SIMD implementations is a very complex process that requires an entire core redesign. The Palomino had an entirely new core layout compared to the T-bird. While I do think originally SSE was delayed for marketing purposes (AMD wanted their 3dNow! to take over), I think they quickly became realistic about who controlled the software developers. Think about it, the Palomino had a complete core redesign in order to incorporate SSE. Hammer is yet another core redesign. Keep in mind you're not just designing an implementation, you have to incorporate it into a current design.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.