Transmeta chip shows Athlon64 flair

[Spitfire_x86]

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[Schmide]

As seen inthe <A HREF="http://www.theinquirer.net/?article=8214" target="_new">inq</A>, AGP is on the docket as well.

Dichromatic for your viewing plesure...

 

[Crashman]

Yes, in fact the northbridge could be made completely useless by connecting hypertransport to a 3GIO controller (traditionally in place of the southbridge). Hehe, the best of AMD and Intel.

<font color=blue>Watts mean squat if you don't have quality!</font color=blue>

 

[eden]

What in the world would an on-die AGP controller provide more?

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[Crashman]

3GIO is faster than AGP8x. Hypertransport is supposed to be fast enough to host a 3GIO bus. So if a CPU had it's own Hypertransport connection and memory controller, no AGP needed, no northbridge needed.

<font color=blue>Watts mean squat if you don't have quality!</font color=blue>

 

[Twitch]

Wasn't Hammer supposed to essentially eliminate the Northbridge? It seems like I read that a loooong time ago.


<-----Insert witty sig line here.

 

[eden]

Still, what advantage would there be?

More bandwidth? HA! (and you know the answer pretty well to this)

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[Crashman]

How about making AGP, PCI, and sever versions of PCI all obsolete and replacing them one one slot, PCI express?

<font color=blue>Watts mean squat if you don't have quality!</font color=blue>

 

[juin]

on the future AGP port will be disapear and they will replace it by 3GIO link and hub

[-peep-] french

 

[eden]

Ok sure, that is great, but it still does not answer my question about an on-board AGP port's advantages.

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[Spitfire_x86]

Is 3GIO and PCI-Xpress same thing? Or 3GIO is more advanced than PCI-Xpress?

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[juin]

PCI-Express is the 3 generation of O/I also know as 3GIO (3 generation I/O).

PCI-X is a pci regular update.

[-peep-] french

 

[zeexen]

Is the pci-express (like the AGP) only reserved for the graphic cards?
Or will it work also with the other cards: gigabit-nic,...?

If I buy the boxed version of the "hammer", will I get a box of nails for free??

 

[juin]

no all connection exception to Nortbridge to CPU northbridge to Memory

[-peep-] french

 

[juin]

This is a lack of knowlege from the website intergrate MCH as been develope in Tinma (intel) and EV7 way before AMD have figure what is a memory controleur.

[-peep-] french

 

[juin]

reduce the number of pin and wire on the mothers board but increas the nb of pin inside the package and increase the heat inside the cpu.Also cut lantency for the card to access the ram.

[-peep-] french