A theory on a double renaming logic on presscott

[juin]

http://www.chip-architect.com/news/2003_03_23_Prescott_doubles_inflight_uOps.html

It a part of the OoO engine but each tread in a P4 need about 128 register to be able to reach the max output of 4 instruction cycle.

So may 2 tread may want 2*128 register but in real life about 3/4 are just buble in the pipeligne but it may give better control on HT and others improvement that i dont know.a 4 way SMT become a theory also on nocona

[-peep-] french

 

[slvr_phoenix]

<A HREF="http://www.chip-architect.com/news/2003_03_23_Prescott_doubles_inflight_uOps.html" target="_new">Clickable...</A>

And the news doesn't seem to be anything new to me.

<font color=blue><pre>If you don't give me accurate and complete system specs
then I can't give you an accurate and complete answer.</pre><p></font color=blue>

 

[juin]

they move to share to dedicate to each tread

[-peep-] french

 

[LumberJack]

Is this the same scheme used in Itanium and Xeons?

To err is human... to really screw things up you need a computer!

 

[juin]

no itanium that have renaming register as he dont have OoO engine.

Xeon have the same number 128.But nocona seento have 512 wichs twice as much as Presscott.

[-peep-] french