lhgpoobaa

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Dec 31, 2007
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The Tbred only had one L2 cache size, 256k. The barton has 512k.

The tbred however came in two distinctly different forms, the TbredA, limited to around 1800-1900Mhz, and the TbredB, which can reach 2200 - 2500Mhz.

<b>Now can someone explain how we ever got the idea that baby bunnies lay multicolored eggs made of chocolate in our living rooms?" :lol: </b>
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soulprovider

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I guess they don't but maybe the elves wrap the droppings in nice shiney paper cos it's pretty and Mum won't hit the roof when she see's it.

btw, do you reckon the large ones are the ones with 512k L2 cache?

<b>Vorsprung durch Dontwerk</b>.....<i>as they say at VIA</i>
 

lhgpoobaa

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Dec 31, 2007
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yep. you have to put the extra circutry for the cache somewhere! the barton is a bigger die size.

<b>Now can someone explain how we ever got the idea that baby bunnies lay multicolored eggs made of chocolate in our living rooms?" :lol: </b>
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soulprovider

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Problem is that would mean less eggs per wafer unless AMD fed their rabbits more?

<b>Vorsprung durch Dontwerk</b>.....<i>as they say at VIA</i>