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Aces hardware on Power consumation of Opteron

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http://www.aceshardware.com/read.jsp?id=55000266

A figure or estimation of power consumation.

Around 50 watt to 60 watt.AXP use 62 at the same speed.

[-peep-] french

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pretty impressive chip i say. far better then the pentium 4. but the pentium 4 is older than the opteron so that is kind of like a "duh". how about we compare athlon xp to the k6-2? slightly stupid right. the comparison if anyone wants to make one will be prescott and the opteron.

Life is irrelivent and irrational.

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Reply to xxsk8er101xx

<A HREF="http://www.aceshardware.com/read.jsp?id=55000266" target="_new">Aceofclick</A>

Dichromatic for your viewing plesure...

Reply to Schmide

pretty impressive chip i say.

No less improvement that Nw to Presscott.
There a platform improvement like EV7 .

It will be nice to compare a Xeon MP 2.2 166 FSB QDR(dont exist and will never exist) and a Opteron 1.8 as there use the same prosscess same transistor count and have about the same headroom of clock speed over them also same memory type DDR 333 or put DDR 266.

Nocona wont be offer until Q1 or Q2 of 2004 it let AMD with a 6 month perf advantage on some test that will grow until Nocona is release (((((some test win by Xeon may fall equal to a opteron futher on timeframe)))).

[-peep-] french

Reply to juin

Quote :

but the pentium 4 is older than the opteron so that is kind of like a "duh".

That absolutely made no sense.
The Pentium 4 IS NEWER than Opteron ever will be. The P7 core is far more advanced than the K7-K8 is. You compare the best of the best in the segment, and here the Xeons are P7s. Additionally, Intel's processes have better overall temp and heat consumption, save for the 3.06GHZ, so you're still not making sense.

Quote :

prescott and the opteron.

Prescott is desktop, Opteron is server. Prescott is 0.09m, Opteron is 0.13m SOI. Prescott has no MP capabilities, Opteron is made to serve.
What the hell man?

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Reply to eden

when did the opteron come out and when did the pentium 4 come out?

Women defines the word irrational!

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Reply to xxsk8er101xx

right your being an extremist here. opteron or athlon64 or sludgehammer. whatever dude.i'm not a [-peep-] engineer so get over yourself. you knew what i [-peep-] meant.

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Reply to xxsk8er101xx

Opteron still is a K7 architecture that is as old as Older Katmai P3.P7 start with willimete.

K9=EV8 on X86-64 ????

[-peep-] french

Reply to juin

When comparing two CPU's, clock speed is not important. But when we should compare two CPU architectures, then we should compare clock vs. clock. K7 wipes any kind of advantage of P4 in equal clock speeds, K8 increases the performance lead.

IMO, K8 vs. P7 is Itanimum2 vs. Opteron. Itanium2 is a better CPU, so it can beat Opteron in some cases with much lower clock speed. And Opteron beats Itanium in it's strong areas (Integer) with much higher clock speed. But since we don't buy architectures, we need practical solution for everyday use, this is why P7's are worthy competeitor of K7/K8, Opteron can think about grabbing some Itanium market share.

Currently, K7/K8 is the limit of x86.

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Reply to Spitfire_x86

i think i see what your saying. (you really need to work on your english lol ;p)

BUT! as they say, if it isn't broken don't fix it. Clearly the k7 core has been a success and AMD just approved on it. so it is newer then the pentium 4.

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Reply to xxsk8er101xx

No, they just updated a bit of it. The P7 is a total change, practically NOTHING is of the P6. And if I may say so, it is the most interesting architecture of the two, mainly because it is there for any future improvements, it is ready. With a 20 stage integer and ~30 for FPU, adding FP units and many other things is easy because you will scale regardless of IPC raising.
The P7 is still the newest core.

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Reply to eden

hmmm alright. what do i know...

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Reply to xxsk8er101xx

Both the FP and Integer pipeline of the P7 core is 20 stages. Intel has traditionally used the same pipeline stage for both the Integer and FP pipelines whereas AMD uses a longer FP pipeline than they do Integer. This was one of the reasons the Athlon scaled better than the P3, the Athlon's FP pipeline was 15 stages while the P3's remained 12. Intel's approach is simpler from a design point of view but I personally think the Athlon's approach is more effective. Minimize Integer branch penalties while allowing scalability from the operations that normally limit scaling the most (FP operations).
As for the P7 design. It's most definitely the more "future-proof" of the two. Later revisions towards efficient use of its execution resources (or, alternatively, addition of more execution resources) can be added without much restraint save budget considerations and the same scalability can still be maintained.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

Reply to imgod2u

I could've sworn having read something of the FPU pipelines being longer than 20.

And yes the Athlon is still more effective, though we could say the same for comparing any core prior to K7 which has less pipeline stages. It has to move on at some point, as we know that x86 just isn't like IA64 for compensation of IPC for clock.

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Reply to eden

no P4 use longer FPU pipe ligne as I2.All instructon lantency must be account.FPU ops lantency is allwayse higher even on a I2.Close to 30 even longer on presscott.

I just know by heart I2.

1 stage for INT 3 for FPU 5 when 82 is enable.1 for L1 5 for L2 including L1 own stage.

I know that you know that.(that good eng)So what you try to mean.

[-peep-] french

Reply to juin

Instruction latencies could usually be done with multiple passes through the FPU rather than separate execution stages. I've tried to google for this and have scoured Intel's website, nothing, not the block diagrams, not the descriptions for each pipeline stage suggests that the FP pipeline is longer than the Integer.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

Reply to imgod2u

I also searched hard on Intel's website and found nothing. Not even Ars Technica. I can't believe they don't divulge such info!

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Reply to eden

It's more likely that the FP pipeline is the same as the integer pipeline. Everything I've read have always treated them both as if they were the same in length. I will ask around to see why there's a difference, as the block-diagram suggests that the execution stage of both Integer and FP take one stage to do.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

Reply to imgod2u

How would it take one clock tick only? It comes as a surprise to me, since most FPUs are pipelined for better scalability and efficiency. Is the Pentium 4 really thinking deeply when it does FP ops?

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Reply to eden

I said it takes one stage, not neccessarily one clock. Operations are often done in the FPU through multiple passes (they go through the same stage multiple times). If this is pipelined (i.e. the next operation can still be issued by the issue port and utilize the part of the FPU that isn't used while the previous operation was calculated by another portion of the FPU), this should produce the same result. I'm not sure how this would affect the instructions-in-flight, maybe it doesn't effect it since the pipelined execution in the FPU isn't out-of-order (once it enters the FPU and begins execution, it can't be re-ordered) so it may not need to take an extra space in the re-order buffer.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

Reply to imgod2u

1 there moe that just 1 ligne of pipeligne even Cache memory got pipeligne.Even on Int there more pipeligne when use a complex divider compare to a simple + or -.

You cannot put a stage at 3 cycle or so it must have a path.

Exception to FPU divider code wich dont have pipeligne in P4

[-peep-] french

Reply to juin

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