Intel moved Tejas up for 2nd half 2004, right? One year or so after Prescott. That's sooner than expected. I just got it: this is too fast! Prescott is designed to fade out at 5.5Ghz or so, and Tejas scales all the way up to 9.5Ghz or so, right? Isn't that absurd?
If Prescott scales to 5.5Ghz from 3.4Ghz launch in 12 or so months, that means it'll go up 200Mhz every month! Intel would have to launch a speed-bumped CPU every two months or so (frequency bumps increase to 400Mhz/bump!)! What is going on there? I don't get it. This means that, by early 2004, we'll have to be well into 4Ghz processors... (hey, I'm not complaining or anything - isn't that one hell of a roadmap?) Plus, Tejas might be 65nm... Strange, my brain can't even cope with that... Maybe AMD is on to something? Maybe Intel has 64-bit support - Yamhill - not on Prescott, but on Tejas? And they are rushing it?...
Will Intel alienate some customers buy introducing faster CPUs too soon?
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<b><font color=red>Three great virtues of a programmer are: laziness, impatience, and hubris.</font color=red><b>
Just because a chip <i>can</i> scale to a higher speed doesn't mean that it <i>will</i>. Intel may very well just release the newer chip at lower speeds. The speed ramp could stay exactly on schedule in spite of any cores coming out sooner.
"<i>Yeah, if you treat them like equals, it'll only encourage them to think they <b>ARE</b> your equals.</i>" - Thief from <A HREF="http://www.nuklearpower.com/daily.php?date=030603" target="_new">8-Bit Theater</A>
You mean that maybe Tejas will be introduced at speeds at which even Prescott could be clocked, i.e. sub-5Ghz speeds? Yes, that's an interesting proposition. And then, prescott could end up still ramping up in speed, but acting like the value line. Makes sense. Good proposition.
In that case, Intel would have lots of cards to play and a lot of breathing room for 2004. They could match AMD's speed and always be only a tad faster, in order to avoid monopoly/antitrust laws, right?...
And when you think about it, really, Intel has been doing this for a while now anyway. I mean look at the Northwood core. It had extra room that Intel hadn't planned on utilizing until AMD delayed the A64 so much that they didn't have much choice. So Intel changed their roadmaps and released the Northwood Cs.
So it really wouldn't surprise me at all that Intel is setting themselves up to have a lot of unused headroom available in their cores. It allows them to both be prepared for a quick speed jump should AMD suddenly become competetive again, and it also allows them to delay releasing a newer core with a higher IPC should AMD's performance become so uncompetitive that Intel fears gaining too much market share.
Intel is definately playing the conservative game now. AMD caught them with their pants down once, but I doubt that we'll ever see anything like that again. Intel seems to be prepared for anything lately.
"<i>Yeah, if you treat them like equals, it'll only encourage them to think they <b>ARE</b> your equals.</i>" - Thief from <A HREF="http://www.nuklearpower.com/daily.php?date=030603" target="_new">8-Bit Theater</A>
Or, just like the move from the P3 to the P4, processor speeds could begin scaling more. I.e. instead of having 200MHz gaps in speed grades, we have 400MHz gaps between speed grades.
During the time of the P3, processor speed grades were differentiated by 66MHz at a time (650, 733, 800, 866, etc.). When we moved to the P4, that changed to a 100MHz gap (1.3, 1.4, 1.5). When we moved to the P4-A, that changed to a 200MHz gap (1.6a, 1.8a, 2.0a, 2.2a). With the release of the P4-B, we seemed to have 133MHz gaps (2.26b, 2.4b, 2.53b). There's no reason to believe that the gaps won't increase with Prescott and Teja. They won't be releasing more processors more often, they'd just release them at speed grades that have greater gaps.
"We are Microsoft, resistance is futile." - Bill Gates, 2015.
Maybe so, but that doesn't detract from the possibility of Intel leaving a lot of headroom free and doing speed bumps only as often as needed.
Anyway, I think that the increase of each bump is reasonable. First of all, you use multipliers, and as the FSB increases, each multiplier bump increases too. Also, there would be no point in increasing a 5Ghz Processor by 66Mhz to 5.06Ghz, 5.13Ghz, and so on...
Right-- obsolete too soon (obsolete faster than normal), and technology creep may keep a number from buying early.
But that's the smart thing to do anyway. I wait until the end of a platform life cycle to buy it. That way, I am assured the best possible performance from that platform.
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<b><font color=red>Three great virtues of a programmer are: laziness, impatience, and hubris.</font color=red><b>
Just like you said, it would be absurd to raise the clock by so little, as the current 200MHZ. Think about it, 5.2, 5.4, 5.6?
Not only this, but the real reason behind it, is the proportional scaling. From 4 to 4.2 you only add a max of 5% of performance with a 5% clock raise (assuming the FSB is perfectly holding it, and no other performance increases will appear until Tejas). Further on, from 5 to 5.2 you add only 4%.
It is only LOGICAL that they add 400-500MHZ per step starting from 5GHZ, and 300-400MHZ by 4GHZ.
So basically it is normal, really. AMD had to raise the per-step clock rise since the 2GHZ, because adding 66MHZ as usual, save for the core upgrade small clock rises, is gonna do jack for competition.
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That was exactly my point... So maybe, if Intel wants to fade out prescott at its full capacity, we´d see bigger speed bumps.
Anyway, if the FSB goes up to 1066, which it probably will after 4+Ghz has been reached (that´s 4x266) then the speed bumps ought to be, at the very least, 266Mhz...
Yes, and it should not be a surprise that an Athlon, if it ran at 3.5GHZ, can still compete against a 5GHZ P4. It's only proportions here.
Of course apps that like raw clocks will enjoy the P4 tons more, but that's the fault of crap programmers who don't know how to program for IPC parallelism.
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Right... The only thing is that Intel's next big core has huge scaling potential (it can do a +65% on clock or so), while AMD's next big score is 130nm... How will A64 scale, btw?...
Can the 130nm A64 scale beyond 2.5Ghz? If not, AMD really needs to get that 90nm tech going by 1st half 2004... Oh well, we'll see how things unfold.
Don't forget Tejas goes to 65nm with 1.2 FSB. Maybe with the early release of Tejas we can see normal pricing of chips like $500 or less on release date instead of $637. since they will be releasing a bunch of new Cpu.
that's the fault of crap programmers who don't know how to program for IPC parallelism
Taking advantage of parallelism is not easy with x86. It can only be done indirectly. As far as x86 is concerned, there is no parallelism. As the programmer saying goes, "Premature micro-optimization is the root of all evil." That's why, as a programmer, IA64 is so exciting to me. Anyway, my point is blame x86, not the programmers. You can blame programmers for bugs and lots of other stuff, but not for not taking of advantage of parallelism. There's not a lot that can be done with x86. Besides, unless you're programming in assembly, the compiler should take care of most of the micro-optimization for you. Sorry, I just had to go on that little rant.
No I totally am cool with that. I do prefer a programmer's input above all on this.
I do however have a small thing against some of them, after experiencing some of the crappiest game programming seen to date, in games like Commanche 4 and Splinter Cell.
I realize graphics programming is not the same, but you get the analogy.
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