2Ghz opteron vs 3.2Ghz P4

AMDzone has a review of a 246 opteron (1p 2ghz and 400fsb) vs 3.2ghz P4, opteron only has cas2.5 memory, P4 and athlon have cas2.

it is the most promising thing i have seen (from amds point of view) for ages, it really beats the p4, and if it had cas2 it would probably have won every benchmark, in terms of pricing a 146 will be similar to a p4 3.2ghz, but mobo and memory are more expensive.

anyway GO AND READ IT, suddenly a 2.4ghz Athlon 64 with cas2 and dual channel looks like it would be much more powerfull than any p4, plus according to inquirer A64s use same power as tbreds at same clock, which means opterons/A64s will have no power issues, and compared to prescotts will be cool runners.

Also, this is all on 32bit, 64bit is meant to have 10-15% more performance according to AMD!!!!!!

Also, in a thread at aces hardware, someone shows how opteron scales much better than p4, read that to.
31 answers Last reply
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  1. can you post a link to the amd zone article...i am feeling a tad lazy...

    If i put my k6 in a Ferrari it would be faster than your your pentium 4 or Athlon XP :tongue:
  2. <A HREF="http://www.amdzone.com/articleview.cfm?articleid=1328" target="_new">link</A>
  3. Thanks.

    :smile: Good or Bad have no meaning at all, depends on what your point of view is.
  4. interesting...these look like very promissing results for amd...i only hope that the a64 performes in a simular maner....

    If i put my k6 in a Ferrari it would be faster than your your pentium 4 or Athlon XP :tongue:
  5. 940 pin model is expected to be re-badged opteron so it would be hard to imagine it would perform any worse.

    registered memory thing is really annoying though isnt it.
  6. Yes it is, though maybe someone around here who has a better understanding of memory than I do might be able to take a guess at how much of a performance gain we might see going from registered 2.5 to the everyday 2? At any rate, I thought it showed some pretty nice performance increases with the improved speed. If they release a 2.2G desktop model at the right price I would be tempted come september.
  7. i think there is meant to be a 2.4ghz model!! now that would seriously kick ass, whether it is available straight away is a different matter though.
  8. Registered memory should be basically on par with regular memory in terms of actual performance. People usually say there is a 1-2% difference. It basically means that the ram has internal registers for checking integrity of the data. In terms of the difference between 2.5 and 2 cas latency. There could be as much as a ~20% difference in some transfers. (I.e. 2.5 is relatively 25% more than 2, or 2 is 80% of 2.5). This does not mean that the benchmarks will sway by ~20% but a DDR400 cl2.5 will basically perform close to a DDR333 cl2 in random access (80% of 400 is 320), while perform basically like a DDR400 cl2 in large (greater than 8 tick transfers). A tick penalty in a 64 tick transfer is less than 2% difference, while a tick penalty in an 8 tick transfer is close to a 10% difference.

    Edited relative %

    Dichromatic for your viewing plesure...<P ID="edit"><FONT SIZE=-1><EM>Edited by Schmide on 08/09/03 12:57 PM.</EM></FONT></P>
  9. Yes, this looks interesting... Won't the A64 be introduced @ 2.0Ghz? Not bad... But Intel will probably get prescott out on time too... @ 3.4Ghz, and with an alledged 15-20% IPC gain over Northwood...

    It's still hard to say anything conclusive at this point...

    :evil: <font color=red><b>M</b></font color=red>ephistopheles
  10. yeah i guess any performance gain from the A64 over the P4 may be short lived due to prescott, but i bet the A64 will give much better performance for the amount of money.
  11. crucial memory
    512mb pc3200 ecc registered = £82.99
    512mb pc3200 non parity = £67.99

    hhhmmmmm , registered is probably better quality, but it is 22% more £.
  12. doesn't ecc take away something like 25% of the memory bandwith...i think i heard this but i really don't know anything about ecc registering...

    If i put my k6 in a Ferrari it would be faster than your your pentium 4 or Athlon XP :tongue:
  13. Since we're talking about opteron reviews, gamepc put one up yesterday as well. <A HREF="http://www.gamepc.com/labs/view_content.asp?id=asussk8n&page=1" target="_new">http://www.gamepc.com/labs/view_content.asp?id=asussk8n&page=1</A> It's only a 1.6 and is using 2100 but it is interesting for comparison.
  14. Well, it might be a good idea to check for other reviews... I'm a bit afraid to judge the hardware scenario based on a site called "amdzone" anyway...

    :evil: <font color=red><b>M</b></font color=red>ephistopheles
  15. I drop by AMDzone about once a week and while they are slightly biased (as in they always seem to try and put the AMD chips in the best light) I've never had any major problems with them. I don't remember their benchmarks ever being that far off from what's been done on another site, and as long as I can continue to get good comparisons between them and other sites I'll keep going back.
  16. i am a bit weary of the title too...but they did show the 3000 with a significant lag behind the p4...so i think there benchies seem somewhat reliable...

    If i put my k6 in a Ferrari it would be faster than your your pentium 4 or Athlon XP :tongue:
  17. I would think they would put the error correcting circuitry on the stick and even if it wasn't on the stick, it's not all that hard to correct the bits when you get the data.

    In any case, you get the address you want, the bits go through ECC circuitry first which is a pretty simple algorithm, then you get the actual bits back.

    Now that I think of it, the ECC circuitry would probably be on the memory controller. And if that were the case, then that means you need the bits your after + the parity bit or ECC bits when you access memory. I forgot the actual number of bits checked for every additional redundancy bit but it might be something like 3 parity bits for every 8 data bits and as the numbers go up you get a better ratio? I'm too lazy to look it up and just going off of what I remember.

    In any case, I think the bottom line is there's a very slight performance decrease when correcting the bits and a noticeable memory bandwidth decrease due to redundancy bits.

    Maybe someone with more specialty in the area could correct this :).
  18. ecc must be enabled in the chipset/memory controllor and the actual memory itself being used...

    If i put my k6 in a Ferrari it would be faster than your your pentium 4 or Athlon XP :tongue:
  19. If AMD drops a 2.4 GHZ hammer and Prescott is delayed

    UH OH

    since your not an INTELLIOT i am sure u wont try to ATTACK AMD ...you will just eat your crow and dream of prescotts that dont bake cookies on them

    but mark my words... INTELLIOTS will not take AMD being top dog lying down... they will start the standard AMD SMEAR campaign
  20. smear campaign? thats a bit hypocritical as you have blatantly been smearing intel.

    also, 2.4 will come later, is not available from launch
  21. You're correct dude...AMD have revised the <A HREF="http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26094.PDF" target="_new">'BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD Opteron Processors'</A>

    Section 3.6.5 it starts talking about ECC.

    <i>The memory controller implements two ECC modes: normal ECC and Chip Kill ECC. These error
    checking and correction modes can only be used if all DIMMs are ECC capable. Chip Kill ECC is
    only available on the AMD Opteron™ processor.</i>

    They have also revised <A HREF="http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25112.PDF" target="_new">Software Optimization Guide for AMD Athlon 64 and AMD Opteron Processors</A> for the uber techs.

    <font color=purple>Ladies and Gentlemen, its...Hammer Time !</font color=purple>
  22. what i would like to know is what ecc's effect on memory bandwith is...looks like i will have to google it...

    I know however that ecc can recover data with single bit errors...if there are 2 bit errors in a row...ecc is not gonna help...this is diffrent from parity in the fact that ecc does something to fix the error where parity just agnologes that an error has occured...i am guessing however that the max bandwith is 10% or more lower than standard dimms...however on the A64...i beleive you will be able to use standard memory...

    If i put my k6 in a Ferrari it would be faster than your your pentium 4 or Athlon XP :tongue:
  23. "These error
    checking and correction modes can only be used if all DIMMs are ECC capable"

    doesnt that imply that if the memory isnt ecc capable then it simply wont function using ecc, in other words there would be no performance loss?
  24. <A HREF="http://wwwcsif.cs.ucdavis.edu/~kwonga/ecs154a/Error_Correction_Code.pdf" target="_new">this seems to be a nice pdf on the subject</A>

    they say a realworld performance hit of 2-3%...but i want to know the actual number...

    If i put my k6 in a Ferrari it would be faster than your your pentium 4 or Athlon XP :tongue:
  25. actually according to this write up...all parity memory modules are ecc capable...i am skeptical on this....but they say that it is possible and i don't have any info to contradict them so i cannot argue...

    If i put my k6 in a Ferrari it would be faster than your your pentium 4 or Athlon XP :tongue: <P ID="edit"><FONT SIZE=-1><EM>Edited by piii_Man on 08/09/03 08:03 PM.</EM></FONT></P>
  26. Quote:
    If AMD drops a 2.4 GHZ hammer and Prescott is delayed

    If this happens, then AMD will have the best processor on the market, period. However, AMD has no intention of dropping a 2.4Ghz Hammer at its launch and Intel has not shown any indication of Prescott being delayed.

    :evil: <font color=red><b>M</b></font color=red>ephistopheles
  27. Whats the matter up too late last nite on Tom's?
  28. Nope. I have not seen any delays. Cept Scotty may launch with 3.6 Ghz
  29. Dark_Archonis brought an interesting argument to this forum, though I don't know if it's true: prescott raises heat dissipation by only 14W for each Ghz clock increase. This means that part of prescott's heat dissipation is clock-independent... consider, say, a 3.4Ghz Scotty @ ~100W heat dissipation, and you'll get the approximate formula: (14*clock + 50)W heat dissipation, linearly approximated. This is good, because it might just allow scotty go to higher clocks...

    I think they will only launch at 3.6Ghz if A64 @ 2.0Ghz proves to be a very serious threat.

    :evil: <font color=red><b>M</b></font color=red>ephistopheles
  30. Well 3.4 than 3.6. Than we go to Grantsdale to bring on the 4.0 Ghz+
  31. The document you're reading is correct.

    All you need to do ECC is the circuitry to perform the ECC algorithm, and the space. Since ECC circuitry is located on the memory controller, then all you need is a memory controller that does ECC and you're set. The problem is that if you run ECC on a non-parity or non-ecc module, you will lose space due to extra bits stored as redundancy bits. So an ECC module will come with the extra space, so that error correction and detection has the extra space. Basically, a non-ecc module with 128mb would lose some of that space to do ecc, however an ecc 128mb module would have extra memory chips on it to account for the error checking/correcting bits.

    Now if that's really possible in practice, I'm not sure. But on paper it should work.

    I think the algorithm described is called hamming codes. The document describes two different types of error checking: parity and hamming codes. Parity is just 1 extra bit calculated and only used to detect 1 error but it cannot correct errors or detect multiple errors. Hamming codes use more bits, but can check for multiple errors and correct one error.

    I'm not sure how it carries on beyond this but I would think that there is wasted bandwidth from the ram to the memory controller. For example, in order to request 12 bits, the memory controller must actually request 16 bits in ECC mode, perform the algorithm, and return the 12 bits. Those aren't exact numbers, just an example.

    From the given information, I think we can deduce that there is some overhead from running the algorithm to do ecc.

    We can also speculate that there might be wasted bandwidth (assuming the bandwidth to the memory controller is the same as what the memory is rated). But you could also fix this by adding a few additional lines for the extra bits sent. So if the standard is 12 bits non-ecc and 16 bits ecc, then you just need 16 bits wide bus and don't use the extra 4 during non-ecc mode.

    This is easy to test if you have an ecc module obviously... just plug it in, run sandra, see if the memory bandwidth differs from a normal non-ecc module. If not, then all you have to test for is the overhead from the ecc algorithm.
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