well the first p4 was the williamette core, which had a 100 mhz bus, socket 432, a .18 micron process and a 256 KB l2 cache. THen there was the norwood core, using a sockry 468 interface, a .13 micron process, a 512 KB l2 cache, and the same 12 KB/8KB l1 cache. The original norwood, p4a, used the same 100 mhz bus, the b used a 133 mhz, and the c used the 200 mhz. A note about intel and amd bus speeds: just as ddr ram effectively doubles bandwidth by transferring data twice per clock cycle, intel's cpu buses transfer data 4x per clock cycle, so the p4a is an effective 400 mhz, the b a 533 mhz, and the c an 800 mhz. Amd uses a similar strategy, but their 200 mhz bus speeds on the high end barton chips are an effective 400 mhz speed, and their 166 give a 333 speed. Celerons are based on pentiums, but they are much slower because of lower bus speeds and cache sizes. Xeons are the high end intel chips, mostly used in 3d workstations and such, and are more different, using a different interface and core architecture.
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