*Let me Fix something here*
The athlon 64 fx like other hammer processors will not have a FSB to system. The traditional FSB we all know is from CPU to memorycontroller and Backsidebus(BSB) is cpu to L2 cache. Since it is integrated the FSB on all hammer processors now depends on the CPU's clock speed. if it is 2Ghz the FSB is 2ghz. That also means that it can support any memory speed type as long as the speed of the ram is not more than the CPU's clock frequency and it's l2 cache throughput(two factors that must not override each other: the bus speed or bus width)... The integrated memory controller is then connected to the "memory Bus". This can be 100,133,166,200 DDR depending on AMD to what ram speed they will like to support these days. On like todays fsb's the cpu is connected to the northbridge 'memory controller' and then to the 'memory bus'. This is also limited because as cpu clock speed grows latency does not reduce. FSB remains the same. Also this only allows one read/write opteration per cycle. That means that you cannot read and write at the same time no matter how much bandwidth you have*(6,4Gb/sec++). But hammer systems don't work like that. The memory bus does not require any distrubance from the system. The cpu and the memory will be happy . If data need to be read from memory it will pass through the cpu and then hypertransport link to the system.(see errata)
Behind the cpu core is a hypertransport Bus. It supports various frequency's. 200/800Mhz DDR upstream/downstream datapads. It can carry various amounts of bits up to 32bits and also more than one read/write operation per clock cycle because it is a serial bus unlike traditional FSB's and is bidirectional. Even 20 PCI-Express devices can be connected without problems! Traditional FSB's today have to share the bandwidth. For example a system with 6.4Gb/sec bandwidth will have to share its bandwidth with the AGP bus e.t.c...but on a hammer system this is done parralel with the hypertranspot bus. its like hyperthreading but on hardware level. Therefore I/O bottlenecks will autotmatically be removed. It can even work with only 3,2gb of bandwidht depending on the memory speed and still support pci-express and the rest. What you can conclude from this is that the 'new' FSB here is the speed of the HTB(hypertransport-bus). todays systems work with 800Mhz DDR clocks and 16bits datapad. That will get you a total of 6,4 gb/sec per sec of total I/O throughput with 3,2Gb/sec upstream and downstream read/write instantly. but with 32-bits datapad it can climb up to 12,8Gb/sec with 6,4 gb.sec up/down.
errata : *Cpu directly to Agp writes do exist *
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<P ID="edit"><FONT SIZE=-1><EM>Edited by pirox on 09/03/03 05:48 AM.</EM></FONT></P>