Spuds Intel Propaganda Campaign *updated*

[spud]

Reserved to when I get back into the loop.

 

[Mephistopheles]

Wow... long post...

I'll come back when I have more time and read it all...

<font color=red><b>M</b></font color=red>ephistopheles

 

[RRAMJET]

just give a link to the site you cut and copied from already...

If he doesn't die, he'll get help!!!

 

[jmecor]

sooooo long post.
i prefered diagrams

<font color=green>If your nose <b>RUNS</b>, and feet <b>SMELLS</b>.
Then you must be born <b>UP-SIDE DOWN</b>.</font color=green>

 

[slvr_phoenix]

Long, but yeah... Intel has been doing some cool stuff with the P4. Imagine if you could take some engineers from both companies and make a completely new product.

<pre><A HREF="http://ars.userfriendly.org/cartoons/?id=20030905" target="_new"><font color=black>People don't understand how hard being a dark god can be. - Hastur</font color=black></A></pre><p>

 

[scamtrOn]

its all from that boys head!! amazing, isn't it?

<font color=orange><b>
sex is bad, bad is sin, sin is forgiven so sex is in

 

[TTZX]

Great post spud, very informative.

_ _ _ _ _ _ _ _ _ _ _ _ _ _
P4 2.4C @ 3.0GHz 1.525V Stock HSF
Abit IS7 BIOS v1.3 GAT Auto
Corsair XMS 512MB TwinX3200C2 2-3-3-6
GeForce4 Ti4200 AGP8X 128MB
Seagate Barracuda 80GB SATA

 

[HardWareBoss]

That would be nice. A new company building Cpu's.

 

[imgod2u]

A few corrections:

1. The L1 data cache is used for only integer/memory address data. All FP data is fetched from the L2 cache. One of the reasons the P4 relies so much on its L2 cache.

2. The L1 cache is also pipelined. Meaning data can be accessed every cycle but it takes 2 cycles for a complete 32-bit integer to be loaded. This wasn't explicitly stated.

3. MMX had some instructions to operate on 64-bit quad operands. They were some logical and/or instructions, no arithmetic.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

 

[eden]

If anyone here needs to wake the hell up and read this, it's Kinney. Where's that boy now?

--
<A HREF="http://www.lochel.com/THGC/album.html" target="_new"><font color=blue><b>Are you ugly and looking into showing your mug? Then the THGC Album is the right place for you!</b></font color=blue></A>

 

[spud]

Imgod2u you best contact Intel on that since thats where I copied and pasted that area. But hey what the hell do they know they only designed the chip.

-Jeremy

<A HREF="http://service.futuremark.com/compare?2k1=6940439" target="_new">Busting Sh@t Up!!!</A>
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[ufo_warviper]

Wow! This post is so long I don't think I am going to be able to abosrb it all tonight. I'll definitely give tis some thorough reading tommorew, and perhaps bookmark this thhread. BTW, Nice Job Spud.

My OS features preemptive multitasking, a fully interactive command line, & support for 640K of RAM!

 

[spud]

Hehe wait till you see my Itainium one man oh man dats the real keeper. Probably take me a day or two to proof. Do a better job that this one though ive noticed some more spelling grammar and sentence structure errors. Gotta get on those tomorrow this is a propaganda war.

-Jeremy

<A HREF="http://service.futuremark.com/compare?2k1=6940439" target="_new">Busting Sh@t Up!!!</A>
<A HREF="http://service.futuremark.com/compare?2k3=1228088" target="_new">Busting More Sh@t Up!!!</A>

 

[coolsquirtle]

BORING

kidding spud, great job, much better than my crappy buying guide

Proud Owner the Block Heater
120% nVidia Fanboy
PROUD OWNER OF THE GEFORCE FX 5900ULTRA <-- I wish this was me
I'd get a nVidia GeForce FX 5900Ultra... if THEY WOULD CHANGE THAT #()#@ HSF

 

[imgod2u]

Intel's Pentium 4 Manual makes it quite clear that there are MMX 64-bit instructions (logical). The Optimization Manual makes it quite clear all FP data is loaded from L2.
This can be found on their website.

http://www.intel.com/design/pentium4/manuals/245471.htm
http://www.intel.com/design/pentium4/manuals/248966.htm

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

 

[TTZX]

Spud, do you know what changes are being made to improve Hyper Threading or are the improvements going to come solely from the changes you already mentioned?

_ _ _ _ _ _ _ _ _ _ _ _ _ _
P4 2.4C @ 3.0GHz 1.525V Stock HSF
Abit IS7 BIOS v1.3 GAT Auto
Corsair XMS 512MB TwinX3200C2 2-3-3-6
GeForce4 Ti4200 AGP8X 128MB
Seagate Barracuda 80GB SATA

 

[Groveling_Wyrm]

Yeah, call it a "Pentathlon". That way it would run good in 5 different benchmarks! LOL!!!!

:tongue:

<font color=blue> Ok, so you have to put your "2 cents" in, but its value is only "A penny's worth". Who gets that extra penny? </font color=blue>

 

[traviss187]

although it's REALLY long and I havn't gotten all the way through.. I can say I was relieved by this fact and the post wasn't "prescotts going to kick some ass and be really cool because the opteron sucks and is made by amd"
articles like this are why I read these forums.. so I can actually learn things, if I wanted a pissing contest I'd walk down the street to a bar.. speaking of which I have to go now

 

[spud]

Big thing as far as I can tell from the available info from Intel and Jack Lo, Henry Emer and Dean Tullsen they are the formost IMO in the theory of Hyper Threading technologies.

With the issue port inscrease and the completely seperate L1 caches as well as the two rapid execution units to feed those caches there shoud be substancial improvements. Occording to what the whitepapers studies and thesis papers say that substantial increases in hyper threading operations are expected from these improvements.

As far as I am concerned this is extremely exciteing technology. With talk that Nocona will be able to do 4 threads instead of two makes it even more exciteing. The Prescott will soar thats for damned sure. By how much over the Northwood is still yet to be seen but I easily see 20%+ accross the board. But thats only my opinion based on my own observations on how the P7 reacts to cache size increases, issue ports, FSB speeds, and register adjustments.

-Jeremy

<A HREF="http://service.futuremark.com/compare?2k1=6940439" target="_new">Busting Sh@t Up!!!</A>
<A HREF="http://service.futuremark.com/compare?2k3=1228088" target="_new">Busting More Sh@t Up!!!</A> <P ID="edit"><FONT SIZE=-1><EM>Edited by spud on 09/10/03 11:29 AM.</EM></FONT></P>

 

[spud]

Imgod Im sorry I missed that I dont program yet so that Optimization Manuals are pretty useless to me but I think ill sit down sometime this week and read all that. I could do a code execution comaparision of the P7 K8 cores for everyones reference. But first thing is pulling my Itainium and Intel Compiler posts up.

-Jeremy

<A HREF="http://service.futuremark.com/compare?2k1=6940439" target="_new">Busting Sh@t Up!!!</A>
<A HREF="http://service.futuremark.com/compare?2k3=1228088" target="_new">Busting More Sh@t Up!!!</A>

 

[spud]

*bump* cant be haveing this fade away there are some changes I made to whats gonna be in the Prescott plus there are stupid people roaming freely in here with out a leash. Gotta spread the word of god for all to see.

-Jeremy

<A HREF="http://service.futuremark.com/compare?2k1=6940439" target="_new">Busting Sh@t Up!!!</A>
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[Schmide]

Dude Highlight your changes. I'm not rereading the whole thing to find one frilling paragraphs worth of infomation.

Dichromatic for your viewing plesure...

 

[ImpPatience]

Thanks, lotta that was over my head, but that was a lot better then "Intel rocks, AMD sucks" or vice versa. As someone new here stuff like this helps to understand what really is going on.

Thanks again!

<font color=blue><b>Purchase object A, install object A, curse object A, repeat...</b></font color=blue>

 

[spud]

I color coded it for you guys, there was just a few minor updates.

-Jeremy

<A HREF="http://service.futuremark.com/compare?2k1=6940439" target="_new">Busting Sh@t Up!!!</A>
<A HREF="http://service.futuremark.com/compare?2k3=1228088" target="_new">Busting More Sh@t Up!!!</A>

 

[jurians]

bump good info..