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Hyperthreading for the A64 in the future?

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September 26, 2003 8:15:07 AM

Could hyperthreading improve the performance of the A64? Would it even be possible for AMD to do this? And if so, do you think we will see it at some point in the future?
September 26, 2003 12:42:47 PM

Hyper-Threading is the only way to increase IPC efficiently, so yes I think sooner or later AMD will have to use it too.
September 26, 2003 4:16:25 PM

AMD is planning to make a dual-core A64 soon, which is their version of HT. <A HREF="http://www.xbitlabs.com/news/cpu/display/20030924042452..." target="_new">Read more @ X-bit labs</A>. <A HREF="http://www.theregister.co.uk/content/61/32986.html" target="_new">The Register</A> is also saying the same thing.

<A HREF="http://www.anandtech.com/mysystemrig.html?id=24106" target="_new">My System Rig</A>
<A HREF="http://service.futuremark.com/compare?2k3=535386" target="_new">3DMark03</A><P ID="edit"><FONT SIZE=-1><EM>Edited by FallOutBoyTonto on 09/26/03 11:17 AM.</EM></FONT></P>
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September 26, 2003 4:52:13 PM

I think you're wrong. Intel is also doing a dual-core system for 2005. But that is not the same as HT at all. HT is not SMT. Intel will be utilizing dual HT-enabled CPUs while AMD will use dual-CPUs, period. AMD NEEDS HT.

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September 26, 2003 4:54:53 PM

They need it ASAP IMO. If the A64 FX per clock is up to 2x as fast (see Ace's 2.8GHZ test against the 2.8C), and it has not even used any of its IPCs effectively, HT will make it devastating.

Athlons have 9 pipelines, and probably don't even use one third right. According to imgod2u's link to HP's tests, an average of less than 1 IPC is used in encoding. I personally believe at least 3 are used in typical rendering or CPU-intensive tasks. Now, we've seen what HT can sometimes do for P4 if multi threading is supported.

Now think of the Athlon's wasted space converted into used space. It already is crushing per clock. Imagine having twice the resources used?
It's ideal, but it can happen. It's only the heat problem here.

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<A HREF="http://www.lochel.com/THGC/album.html" target="_new"><font color=blue><b>This just in, over 56 no-lifers have their pics up on THGC's Photo Album! </b></font color=blue></A> :lol: 
September 26, 2003 5:04:56 PM

Needs it? I doubt it. Might benefit from it? That's a tough one.

I mean of course in theory they would. However reality and theory do not always play nicely together. (Much like our current CPU forum...)

It comes down to CPU architecture. The P4 is becoming extremely dedicated to out of order execution, which makes implementing HT a breeze because there are already the caches in place to keep track of a non-linear flow. The Athlons however are still based on the far more traditional x86 methodologies which just were never intended for good parallelism.

As such there would be an awful lot of new components added to an Athlon's core just to even make HT possible. And then there's actually making HT work <i>well</i>... and with as much effort as AMD has actually put into their prediction and prefetching logic we all know just how many resources AMD is willing to dedicate (or even has available to dedicate?) to those kinds of things.

So from AMD's perspective it'd be an awful lot easier to just ignore HT all together and work on double-cores and such instead. The logic components for that are pretty much already there since it's just literally two CPUs in one die. Where as HT would require AMD to do some serious R&D and make some major changes to their architecture to even support.

In the end I think yes, the CPU itself might benefit from HT, but AMD as a company wouldn't. Too many resources would be spent just to make it worthwhile and there are other much more cost-effective solutions for AMD.

<pre><A HREF="http://ars.userfriendly.org/cartoons/?id=20030905" target="_new"><font color=black>People don't understand how hard being a dark god can be. - Hastur</font color=black></A></pre><p>
September 27, 2003 12:18:46 AM

Correct on the prefetch thing. I think I forgot about it because I seem to recall you or someone here explained the prefetch limits before HT could work well. And it is true prefetch is horrible on Athlons as demonstrated in a special test by Ace. Although one must wonder just how lower can the P4 go now that it is up to 50% the speed of an Athlon in gaming per clock, if you lowered its prefetch abilities.
Indeed they would need to improve it. But then again, shouldn't the core be improved? Is it it not too old-fashioned, and the only things really major in it are some components added? Sure there is a packing stage, but I've yet to see what improvements it brings, as you can count higher clockspeeds out. These are extra stages with extra work, not divided work.

Still, I think above all, the K9 must be a radical restructure (will be AMD's first ever since K6, considering the K7 was NexGen's design not their fruit), with a very long pipeline. Yes the K8 is performing excellently, and 64-bit could make it very much an Intel-killer, but eventually it won't clock far. It's still an old low-stage pipeline design. Intel's fruit may finally reveal its true future-proofness once the K8 wears out completely at the physical limits of 10-12 stage pipelining.
That's when Nehalem busts in.

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<A HREF="http://www.lochel.com/THGC/album.html" target="_new"><font color=blue><b>This just in, over 56 no-lifers have their pics up on THGC's Photo Album! </b></font color=blue></A> :lol: 
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