i'm looking for some infos about the next Intel core...is anyone able to help me? I'm trying to find something like those guides which appeared on the net for the Athlon 64 launch last 23rd of September...i found chip-architect's analisys of Prescott's core but i was looking for something more general...Can anyone help me?
Thank you in advance!
Spud here had made a pretty nice sum-up of what Prescott has. Look for his "Intel propaganda" thread in this forum.
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I do have to add though, that in general, most of that information is either covered or very vague.
Still, there's likely more to be learned from once it hits the market, and sites like Anand dissect it.
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On second thought, here it is. Knock yerself out!
<A HREF="http://forumz.tomshardware.com/hardware/modules.php?name=Forums&file=viewtopic&p=151365#151365" target="_new">http://forumz.tomshardware.com/hardware/modules.php?name=Forums&file=viewtopic&p=151365#151365</A>
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You really believe Spud wrote that ? LMAO ! yeah Spud did a great job of copy pasting from intel's whitepaper while rephrasing a few sentences left and right like those that refered to images he could not duplicate on this forum. A simple examples, quotes from intel PDF:
Quote :
Unlike conventional instruction caches, the
Trace Cache sits between the instruction decode logic and
the execution core as shown in Figure 1. In this location
the Trace Cache is able to store the already decoded IA-
32 instructions or uops. Storing already decoded
instructions removes the IA-32 decoding from the main
execution loop. Typically the instructions are decoded
once and placed in the Trace Cache and then used
repeatedly from there like a normal instruction cache on
previous machines. The IA-32 instruction decoder is only
used when the machine misses the Trace Cache and needs
to go to the L2 cache to get and decode new IA-32
instruction bytes.
Spud turns this into:
" As most of you know the Trace Cache sits between the instruction decoders and the execution core. With that in mind it’s able to store already decoded instructions which move the main IA-32 decoders from the execution loop. Typically the instructions are decoded once and placed in the Trace Cache then used repeatedly from there like a normal instruction cache on previous cores. Unless there is a cache miss then off the L2 for new instructions. "
So if you want to read the original article without the sometimes completely incorrect rephrasing or abbreviations, why not go over to intel's site and read this document:
<A HREF="http://www.intel.com/technology/itj/q12001/pdf/art_2.pdf" target="_new">http://www.intel.com/technology/itj/q12001/pdf/art_2.pdf</A> ?
Sorry Spud.. seems like a huge waste of time
= The views stated herein are my personal views, and not necessarily the views of my wife. =
Of course I can't expect you to understand someone who was interested in the P7 core and decided to share it more vulgarly to the public.
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I call it copyright infringement; he doesnt even link or mention the source, and pretends its his own work.. Its also worse as the original document, so what the use, other than trying to claim someone elses fame ?
= The views stated herein are my personal views, and not necessarily the views of my wife. =
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