How programs work inside a computer?

[varghesejim]

These are my doubts about the internal working of programs. If somebody can clear it please do that.

When we are building an executable file actually we are converting the code to the instructions to the microprocessor. This binary conversion is the duty of the compiler and it will convert the code to instructions for a specific microprocessor. Now how can it work in other microprocessors? I will tell you an example. Consider if the compiler converted the code for Pentium 4, and suppose there are some SSE2 instructions. Now how can I run this executable file in an Athlon XP which is not supporting SSE2?One explanation is usage of an emulator which is inside the processor which is emulating the Pentium 4 instructions. Is there such kind of thing in all processors? But how an executable build with a modern compiler (the code contains SSE2 instructions) is working even the oldest X86 processor which is not even supporting SSE? Does the compiler have to build various branches for various processors?

 

[Woodman]

Well just a guess, but if the program detects SSE2 in the processor, then it'll run SSE2 instructions.

*shrugs*

-----
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[slvr_phoenix]

Optimized code often has processor-specific logic branches so that SSE2 can be run on SSE2 enabled CPUs but isn't a requirement for non-SSE2 CPUs. Sometimes it's a matter of the code using specific DLLS. Other times it's branching in the primary binary itself. But almost always any time you have code for a specific feature like that you also have code to run without that feature.

<pre><A HREF="http://ars.userfriendly.org/cartoons/?id=20030905" target="_new"><font color=black>People don't understand how hard being a dark god can be. - Hastur</font color=black></A></pre><p>

 

[varghesejim]

Post deleted by varghesejim

 

[Cloaked]

whoops

 

[varghesejim]

So if my program uses the MMX,SSE, and SSE2 instructions the compiler have to write code in four ways(branches).One for the newest P4,One for the P3 with SSE one for the pentium with MMX and one for the processor prior to it.So that much of space is needed if you want to optimise code for all the generation of processors.I understand your point.
Now one doubt.I heard that some processors ,specifically RISC ones which have small instruction sets are using emulators onboard to ensure compatability.Do you know which processors are using this technology(any desktop processors?).What are the occations "branching software" and "emulators" are used and what is the criteria for selecting one of the technology for a processor?branching have space complexity high and emulators will make the time complexity high.Right?

 

[slvr_phoenix]

So if my program uses the MMX,SSE, and SSE2 instructions the compiler have to write code in four ways(branches).One for the newest P4,One for the P3 with SSE one for the pentium with MMX and one for the processor prior to it.

The compiler or the programmer, depending on the situation. Some software out there however just ignores older processors. This is why there are things called 'minimum requirements'.

I heard that some processors ,specifically RISC ones which have small instruction sets are using emulators onboard to ensure compatability.Do you know which processors are using this technology(any desktop processors?).

I've no idea which RISC, CISC, etc. would be doing such, if any. I'd hazard a guess at procs for Macs at the very least.

What are the occations "branching software" and "emulators" are used and what is the criteria for selecting one of the technology for a processor?

Branching is pretty much used exclusively in any x86 that wants processor-specific optimizations. I've no idea about the emulators. And the criteria is pretty much if you want to optimize for it. Otherwise just stick to plain old x86/x87 or whatever.

branching have space complexity high and emulators will make the time complexity high.Right?

Branching makes the binaries larger, yes, though not always by much. It depends on how much code is repeated in each branch. And emulators would likely cause a performance loss. Although in theory a hardware emulation layer should run without a noticable performance loss if designed well.

<pre><A HREF="http://ars.userfriendly.org/cartoons/?id=20030905" target="_new"><font color=black>People don't understand how hard being a dark god can be. - Hastur</font color=black></A></pre><p>

 

[varghesejim]

I didnt understand what u mean