Prescott Heat Problem

[Scout]

Has anyone seen any good technical articles on the Prescott heat issue? I've read all the intro reviews and seen the comments on "leakage", "strained silicon" and so forth, but I'm wondering exactly what's going on and when Intel is likely to fix it and how? (I know.. a lot to ask!)

Scout
700 Mflops in SETI!

 

[TheRod]

Simple to fix... Buy a watercooling system at 200$US with the Prescott you will buy.

So your Prescott will be cooler!

The "heat problem" can't be corrected by Intel, the design of the prescott make it dissipate about 100 Watts, so Intel can't do anything about this, they choose to design this processor that way... The only thing they can do for this, is selling lower frequency Prescott or expect that good yields would permit lower voltage to meke them work at high frequency.

And heat is not only the Intel problem, remember the first GeForce FX that needed so big fans and heatsink tu run at acceptable temperature.

And probably, AMD and ATI will face a similar situation when they will switch to new fabrication process with their next generation GPU/CPU.

--
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[Scout]

Yeah, but what is it about Intel's 90 nm process that makes it suck so much power??? Usually a die shrink results in lower power consumption...

Scout
700 Mflops in SETI!

 

[eden]

My money's on the low amount of copper interconnect layers. At only 7 (1 more than NW), Prescott is still not as good as an AthlonXP in controlling its leakage. The Tbred B worked great because they added layers, 3 specifically I believe, and that resulted in it being able to reach a good 2.7GHZ modernly on air, at 0.13m.

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<i>Ede</i>
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[P4Man]

2 things:
1) it is not certain wether Prescotts ultra high power sucking is a result from intels 90nm process, or Prescotts "hyperburst" design or a combination of both. i'm guessing its a combination with the main issue being prescotts design, not the process. once Dothan becomes available, we'll likely have a better idea.

2) process shrinks typically reduce voltage, reduce dynamic power, but increase leakage. On previous generation processes, leakage was not much of an issue, if at all. With 90nm and beyond, leakage will likely become the main source of power consumption, especially using bulk silicon instead of SOI, FD-SOI, or similar techniques to reduce leakeage.

Prescott seems like the "worst case" scenerio today, with a power hungry core (30+ pipeline stages,..), a new smaller process, unexpected high core voltage, and using bulk silicon (intels biggest mistake IMHO).


= The views stated herein are my personal views, and not necessarily the views of my wife. =

 

[TheRod]

90 nm process = less power
higher freq. = more power
transistors count = more power
and so on...

There is a lot of factor that influence power comsuption!

--
Would you buy a GPS enabled soap bar?

 

[Xeon]

and using bulk silicon (intels biggest mistake IMHO).

Please good sir enlighten us on the alternate options available.

Xeon

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[eden]

especially using bulk silicon instead of SOI, FD-SOI, or similar techniques to reduce leakeage.

Those...heheh...
Don't hurt me, I still wuv you!

--
<i>Ede</i>
<A HREF="http://www.lochel.com/THGC/album.html" target="_new"><font color=blue><b>More updates and added sites as over <font color=red>62</font color=red> no-lifers have their pics up on THGC's Photo Album! </b></font color=blue></A> :lol:

 

[eden]

I wouldn't be surprised if the 31 stage pipeline included extra stages, not divided ones. (no longer extending MHZ ceiling like stage division would)
31 is an odd number, thus is definitely not divised from what I see.
Maybe some 64-bit calculation stages were added, who knows.

--
<i>Ede</i>
<A HREF="http://www.lochel.com/THGC/album.html" target="_new"><font color=blue><b>More updates and added sites as over <font color=red>62</font color=red> no-lifers have their pics up on THGC's Photo Album! </b></font color=blue></A> :lol:

 

[jclw]

Here's an interesting post at Ace's Hardware : <A HREF="http://www.aceshardware.com/forum?read=115065211" target="_new">http://www.aceshardware.com/forum?read=115065211</A>

*Dual PIII-800 @900 i440BX and Tualeron 1.2 @1.7 i815*

 

[Scout]

Hummm... can't seem to get to that site right now. I had problems getting to Ace's site a while back. Seems that the site has had some problems. I'll try later.

Thanks.

Scout
700 Mflops in SETI!

 

[jclw]

Works for me:

"LGA 775
By Andy MacKay on Thursday, March 11, 2004 5:10 PM EST

You're correct in a sense, but remember that "voltage" in your post means "voltage as seen at the transistor", which is different than "voltage as seen at the pads" which is what matters to the outside world. Having more pads in the LGA775 sockets means more power and ground pads, which means that to any given part of the chip the effective power loss from outside the package to the chip-level power rails is reduced -- more importantly, the variability of that power is reduced because of lower power/ground inductance and resistance (so sudden current spikes from lots of transistors changing causes less of a voltage variation), so the transistors can run at a lower nominal voltage but still tolerate the inevitable power fluctuations. And this last thing is where you save the power."

*Dual PIII-800 @900 i440BX and Tualeron 1.2 @1.7 i815*

 

[endyen]

That is ok in terms of IR loses, but the problem with scotty is leakage lose. Ie loses from proximity of dissimilar charges. The extra pins will only exacerbate this problem. Actually the extra pins are needed to maintain the point of connection, since the bg config reduces the contact area. I have to agree with Eden, they will have to take a good hard look at current routing to cool this puppy down. If anyone can pull it off though, the guys at intel can.