L2 vs L3 cache

I was in a Computer Architecture lecture at Uni today being told about L1 and L2 cache. He explained that L2 cache was needed because there is not enough room on the cpu for any more L1...but then what is L3? Why not just make L2 cache bigger? I've noticed that AMD don't use it but Intel do.

He gave me some obscure answer along the lines of "it pipelines the speed faster" before admitting he had no idea.

Hey Juin you finally changed your nic.

I aint signing nothing!!!

I didnt get a word of that

P4 2.6@3.38
512Mb PC4000
2x120Gb 7200.7 in RAID0
Waterchill KT12-L30
Abit AI7
Ge-Force4 Ti4200

My understanding is that L3 is slower than L2, and therefore is probably cheaper.

Anxiously awaiting grantsdale...

Lmao! How did you know....

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46,510 , movin on up. 48k new goal. Maybe not..

As usualy, you're talking in a strange mix of swahili and technical buzz words, and the original poster is not likely to understand either.

If french wasnt my second language, so I can reconstruct half your grammar, I wouldnt be able to understand anything of it either. Seriously Juin, if you spend so much time reading and posting here, surely you should be able to write more understandable english by now ? Are you even trying ??

= The views stated herein are my personal views, and not necessarily the views of my wife. =

OK! everybody knows Juin is messing it up with English, but is anyone willing to explain him the cache problem?

>He explained that L2 cache was needed because there is not
>enough room on the cpu for any more L1.

Whoever told you that, is probably out of the loop for a looong time. L2 cache was off die, on the motherboard, in the Pentium 1 days, and earlier. Ever since the Pentium Pro/Pentium 2 it has been on the same CPU module, and since Pentium 3 and Pentium 2 Celeron A it has been ondie, so integrated on the CPU.

Level 1/2/3.. does not say anything on where it is located. The number just refers to its relative position in the cache hierarchy. L1 is closest to the core, typically smallest and fastest. L2 is typically bigger and slower, and 'further away' (both physical, distance, and in latency). L3 is even bigger, slower and further, etc. Some ISA's even have L4 caches, like on the chipset, and if you like, you could consider main memory (RAM) as a level 4 or 5 cache to cache your harddisk.

>Why not just make L2 cache bigger

because bigger typically means slower. Not too mention more expensive (diesize).

> I've noticed that AMD don't use it but Intel do

Intel includes L3 mostly only for its server chips. In multiprocessor configuration, you can never have too much cache, especially with shared bus topology like Xeon or Itanium. You'd typically have 2 or even 4 cpu's using the same memory controller and front side bus, so each cpu's bandwith is cut in half (or by four). To counter this, bigger caches help reducing the need to access main memory.

AMD uses a different approach with its opteron. using an ondie memory controller on every cpu (actually, two controllers per cpu), there is much less need to increase the caches as every cpu has its own memory controllers, and doesnt need to share them with 3 other cpu's. This allows it to access the RAM relatively fast (low latency), and with full bandwith. You could say main memory pretty much acts like a giant L3 cache on an opteron server.

>it pipelines the speed faster" before admitting he had no
>idea.

Exactly, he had no idea. Sounds like uou wasted your time on that lecture .

= The views stated herein are my personal views, and not necessarily the views of my wife. =