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L2 vs L3 cache

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March 29, 2004 4:38:50 AM

I was in a Computer Architecture lecture at Uni today being told about L1 and L2 cache. He explained that L2 cache was needed because there is not enough room on the cpu for any more L1...but then what is L3? Why not just make L2 cache bigger? I've noticed that AMD don't use it but Intel do.

He gave me some obscure answer along the lines of "it pipelines the speed faster" before admitting he had no idea.

More about : cache

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March 29, 2004 11:25:05 AM

Hey Juin you finally changed your nic.

I aint signing nothing!!!
March 29, 2004 12:32:54 PM

I didnt get a word of that

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March 30, 2004 1:54:35 AM

Err...did I actually have my question answered even vaguely there or what? Limited ports? It's cache, it comes with the MOBO.
March 30, 2004 3:46:19 AM

My understanding is that L3 is slower than L2, and therefore is probably cheaper.

Anxiously awaiting grantsdale...
March 30, 2004 4:08:24 AM

To start, cache is now on the chip itself. Because of this, the latency, or wait states are reduced. Cache is usually accessed sequensially so that information held in L3 cache takes longer to get to. Larger cache also tends to have longer latency.
Where a large line 3 cache is very usfull is when most of a program can be held for quick access.
March 30, 2004 9:27:18 AM

I have been repeatedly amazed at the fact He's exactly as readable as he was 2 years ago. maybe he can't actually read or write english at all and just uses babelfish? that would actually make sense :lol: 

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March 30, 2004 9:47:08 AM

OK! everybody knows Juin is messing it up with English, but is anyone willing to explain him the cache problem?
March 30, 2004 10:06:35 AM

Dunno. Does this sound like him:
"I on several occasions was astounded with the fact that it is exactly as readable as it was there is 2 years. perhaps it cannot really read or write English of the whole and the babelfish just of uses? that would be really included/understood".

That is your post bablefished UK->FR->UK
I find it more readable than his posts really :) 

= The views stated herein are my personal views, and not necessarily the views of my wife. =
March 30, 2004 10:21:03 AM

>He explained that L2 cache was needed because there is not
>enough room on the cpu for any more L1.

Whoever told you that, is probably out of the loop for a looong time. L2 cache was off die, on the motherboard, in the Pentium 1 days, and earlier. Ever since the Pentium Pro/Pentium 2 it has been on the same CPU module, and since Pentium 3 and Pentium 2 Celeron A it has been ondie, so integrated on the CPU.

Level 1/2/3.. does not say anything on where it is located. The number just refers to its relative position in the cache hierarchy. L1 is closest to the core, typically smallest and fastest. L2 is typically bigger and slower, and 'further away' (both physical, distance, and in latency). L3 is even bigger, slower and further, etc. Some ISA's even have L4 caches, like on the chipset, and if you like, you could consider main memory (RAM) as a level 4 or 5 cache to cache your harddisk.

>Why not just make L2 cache bigger

because bigger typically means slower. Not too mention more expensive (diesize).

> I've noticed that AMD don't use it but Intel do

Intel includes L3 mostly only for its server chips. In multiprocessor configuration, you can never have too much cache, especially with shared bus topology like Xeon or Itanium. You'd typically have 2 or even 4 cpu's using the same memory controller and front side bus, so each cpu's bandwith is cut in half (or by four). To counter this, bigger caches help reducing the need to access main memory.

AMD uses a different approach with its opteron. using an ondie memory controller on every cpu (actually, two controllers per cpu), there is much less need to increase the caches as every cpu has its own memory controllers, and doesnt need to share them with 3 other cpu's. This allows it to access the RAM relatively fast (low latency), and with full bandwith. You could say main memory pretty much acts like a giant L3 cache on an opteron server.

>it pipelines the speed faster" before admitting he had no
>idea.

Exactly, he had no idea. Sounds like uou wasted your time on that lecture .

= The views stated herein are my personal views, and not necessarily the views of my wife. =
March 30, 2004 12:40:49 PM

Seeing as the he starts off talking about the 4004 or the 8086 and works 'all the way up to the first pentium' I'd say he's a little out of the loop too.



Oh what a tangled web we weave, when first we practice to decieve.
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November 2, 2010 9:39:28 PM

This topic has been closed by Mousemonkey
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