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i need to change useur name.
i need to change useur name.
Mephistopheles
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Mephistopheles
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(Hm, this is somewhat strong indication that Intel's 90nm process is no problem, but prescott's architecture (with a gazillion useless transistors) definitely is.)
Very interesting news on montecito. I was expecting it to be roughly a 2Ghz part, but it seems 2.5Ghz is definitely over-the-top powerful. If it has a dedicated and improved 32-bit emulator, it <i>might</i> even churn out quite respectable 32-bit scores. The current known data for montecito includes:
<b>-Dual Core Chips
-2.5Ghz top core clock (15x166);
-667Mhz FSB (10.6GB/s);
-24MB shared L3 cache;
-Multithreading (2+ threads/core)</b>
Montecito's 1.7 billion transistors (~1 billion cache, 700 million logic) will enable twice the performance, per core, that the current state-of-the-art 1.5Ghz, 6MB cache Madison. If Intel messed around with a dedicated hardware 32-bit execution unit inside Montecito, the adoption of this gargantuan processor will probably be better.
Personally, I expect this will be the first truly interesting Itanium incarnation. As such, heck, it even deserved being called Itanium 3. IA64 research seems stubborn, but Montecito is looking quite good indeed and also at a much higher clock than expected.
If I see things correctly, AMD64 technology-based <i>Toledo</i> will probably be launched at a similar or only slightly higher clock, which is surprising; montecito has a quite high clock. I think it has the potential to outclass Toledo's technology, but it also needs acceptance... Which will be very hard. I also don't see Montecito being delayed at all; Intel has already taped it out a long time ago. If I were at Intel, I'd introduce Montecito ASAP... And put Madison 9M as a bargain Itanium. Maybe by early 2005.
Even if the 32-bit emulation side <i>doesn't</i> get improved, at least the much improved clock and overall design should make up for it and speed everything up quite a lot. Montecito is apparently not only good because it's dual core, but also because each core has apparently been quite enhanced. IA64@2.5Ghz, not bad... It has the highest IPC possible, and given a 67% clock boost, twice the cache per core, a dual core approach, another 67% FSB boost, multithreading, and possibly other core enhancements... It would take Intel's best flopping techniques to make this one a disaster.
<P ID="edit"><FONT SIZE=-1><EM>Edited by Mephistopheles on 08/15/04 01:29 AM.</EM></FONT></P>
Very interesting news on montecito. I was expecting it to be roughly a 2Ghz part, but it seems 2.5Ghz is definitely over-the-top powerful. If it has a dedicated and improved 32-bit emulator, it <i>might</i> even churn out quite respectable 32-bit scores. The current known data for montecito includes:
<b>-Dual Core Chips
-2.5Ghz top core clock (15x166);
-667Mhz FSB (10.6GB/s);
-24MB shared L3 cache;
-Multithreading (2+ threads/core)</b>
Montecito's 1.7 billion transistors (~1 billion cache, 700 million logic) will enable twice the performance, per core, that the current state-of-the-art 1.5Ghz, 6MB cache Madison. If Intel messed around with a dedicated hardware 32-bit execution unit inside Montecito, the adoption of this gargantuan processor will probably be better.
Personally, I expect this will be the first truly interesting Itanium incarnation. As such, heck, it even deserved being called Itanium 3. IA64 research seems stubborn, but Montecito is looking quite good indeed and also at a much higher clock than expected.
If I see things correctly, AMD64 technology-based <i>Toledo</i> will probably be launched at a similar or only slightly higher clock, which is surprising; montecito has a quite high clock. I think it has the potential to outclass Toledo's technology, but it also needs acceptance... Which will be very hard. I also don't see Montecito being delayed at all; Intel has already taped it out a long time ago. If I were at Intel, I'd introduce Montecito ASAP... And put Madison 9M as a bargain Itanium. Maybe by early 2005.
Even if the 32-bit emulation side <i>doesn't</i> get improved, at least the much improved clock and overall design should make up for it and speed everything up quite a lot. Montecito is apparently not only good because it's dual core, but also because each core has apparently been quite enhanced. IA64@2.5Ghz, not bad... It has the highest IPC possible, and given a 67% clock boost, twice the cache per core, a dual core approach, another 67% FSB boost, multithreading, and possibly other core enhancements... It would take Intel's best flopping techniques to make this one a disaster.
<P ID="edit"><FONT SIZE=-1><EM>Edited by Mephistopheles on 08/15/04 01:29 AM.</EM></FONT></P>
(Hm, this is somewhat strong indication that Intel's 90nm process is no problem, but prescott's architecture (with a gazillion useless transistors) definitely is.)
Reply:
Defecting point in Montecito will be high but in 98% wont be fatal as it feature large spare cache.As is be release in 2005 90NM would have mature and with dothan it allready work well.
Very interesting news on montecito. I was expecting it to be roughly a 2Ghz part, but it seems 2.5Ghz is definitely over-the-top powerful. If it has a dedicated and improved 32-bit emulator, it might even churn out quite respectable 32-bit scores. The current known data for montecito includes:
reply
2.5 is lot i think not sure thsi will be avaible at launch.Montecito will be able to overclock itself on low consumation task like commercial load and decrease is clock speed on linpack where about 90% of the resource are use.Benchmarking it will be hard as it clock speed will change base on many factor.Itanium 32 bit perfomance is about equal to a Xeon MP of the same clock speed and teh same cache and bus.SO think about a XEON MP northwood with 24 L3 and 10 GB\S FSB.
-Dual Core Chips
-2.5Ghz top core clock (15x166);
-667Mhz FSB (10.6GB/s);
-24MB shared L3 cache;
-Multithreading (2+ threads/core)
reply:
Intel exec have say montecito will have 3 time the memory performance of Madison.The may sight of 256 bit bus or point to point.Montecito will feature a new protocol in either case it will need a arbitary bus due to dual core.Also suppost to have a 400 FSB version for upgrade for the old systemes.
Montecito's 1.7 billion transistors (~1 billion cache, 700 million logic) will enable twice the performance, per core, that the current state-of-the-art 1.5Ghz, 6MB cache Madison. If Intel messed around with a dedicated hardware 32-bit execution unit inside Montecito, the adoption of this gargantuan processor will probably be better
Reply:
It much more that 1 billion for the cache the cache ^will take about 1.4 to 1.5 billion transistor.Despite legend itanium core is smaller that P4 or Opteron.It might also be the last core to have the hardware IA32.Good thing if you ask me as the IA32 sit in a critical part of the core this will leave a very important place.
Personally, I expect this will be the first truly interesting Itanium incarnation. As such, heck, it even deserved being called Itanium 3. IA64 research seems stubborn, but Montecito is looking quite good indeed and also at a much higher clock than expected.
Reply:
I dont think it deserver the name itanium 3 ît the same core that the original mackinley.Only difference will be Switch on event feature wich is simple and can be put in any CPU without any change to the back end.There might be few change there and there but nothing major.
IMHO Nothing will even close to Montecito in major benchmark.SPEC FP rate will never be outclass except by tukwila.
i need to change useur name.
Reply:
Defecting point in Montecito will be high but in 98% wont be fatal as it feature large spare cache.As is be release in 2005 90NM would have mature and with dothan it allready work well.
Very interesting news on montecito. I was expecting it to be roughly a 2Ghz part, but it seems 2.5Ghz is definitely over-the-top powerful. If it has a dedicated and improved 32-bit emulator, it might even churn out quite respectable 32-bit scores. The current known data for montecito includes:
reply
2.5 is lot i think not sure thsi will be avaible at launch.Montecito will be able to overclock itself on low consumation task like commercial load and decrease is clock speed on linpack where about 90% of the resource are use.Benchmarking it will be hard as it clock speed will change base on many factor.Itanium 32 bit perfomance is about equal to a Xeon MP of the same clock speed and teh same cache and bus.SO think about a XEON MP northwood with 24 L3 and 10 GB\S FSB.
-Dual Core Chips
-2.5Ghz top core clock (15x166);
-667Mhz FSB (10.6GB/s);
-24MB shared L3 cache;
-Multithreading (2+ threads/core)
reply:
Intel exec have say montecito will have 3 time the memory performance of Madison.The may sight of 256 bit bus or point to point.Montecito will feature a new protocol in either case it will need a arbitary bus due to dual core.Also suppost to have a 400 FSB version for upgrade for the old systemes.
Montecito's 1.7 billion transistors (~1 billion cache, 700 million logic) will enable twice the performance, per core, that the current state-of-the-art 1.5Ghz, 6MB cache Madison. If Intel messed around with a dedicated hardware 32-bit execution unit inside Montecito, the adoption of this gargantuan processor will probably be better
Reply:
It much more that 1 billion for the cache the cache ^will take about 1.4 to 1.5 billion transistor.Despite legend itanium core is smaller that P4 or Opteron.It might also be the last core to have the hardware IA32.Good thing if you ask me as the IA32 sit in a critical part of the core this will leave a very important place.
Personally, I expect this will be the first truly interesting Itanium incarnation. As such, heck, it even deserved being called Itanium 3. IA64 research seems stubborn, but Montecito is looking quite good indeed and also at a much higher clock than expected.
Reply:
I dont think it deserver the name itanium 3 ît the same core that the original mackinley.Only difference will be Switch on event feature wich is simple and can be put in any CPU without any change to the back end.There might be few change there and there but nothing major.
IMHO Nothing will even close to Montecito in major benchmark.SPEC FP rate will never be outclass except by tukwila.
i need to change useur name.
Mephistopheles
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I don't know, juin, Intel has never released speed bumps with Itanium. Itanium's current Madison lineup is the same as it was at Madison launch: 1.3, 1.4 and 1.5Ghz speeds... That's what makes me think that it's somewhat likely that 2.5Ghz speeds will be available in 2H05.
You assume, of course, that they did nothing to change that Xeon - I2 clock correspondence in hardware. However, they'd be wise to enhance 32-bit code execution... Even so, well, a Xeon MP with 24MB of cache and 10GB/s FSB would be nice at 2.5Ghz. And the other systemwide improvements will probably also make a difference in execution of 32-bit code.
Hm, a 10.6GB/s isn't three times the bandwidth, so I assume the memory controller has been greatly enhanced and has been made much, much more efficient. Bear in mind that 10.6GB/s is either Dual DDR2-667 (which will be out by then, and possibly with better-than-standard timings) or quad-channel DDR333. Intel has been using quad DDR200/266 for Itanium up until now. I wouldn't be too surprised if at some point they went dual DDR2-667, if they want to promote socket compatibilities for Xeon/Itanium... <wild speculation>I wonder if all of a sudden Itanium had an on-die memory controller? For dual DDR2-667 or quad DDR333? </wild speculation>
That's for sure. IA64 with 24MB of cache, 2.5Ghz? I don't think even any IBM server-class processor will match that easily at all. I think it was P4Man who said that IBM's Power5 @ 1.9Ghz (current existing dual-core design) would not be outclassed by Montecito? Well, enter dual 2.5Ghz Itanium cores, and things ought to change a little...
I don't know, juin, Intel has never released speed bumps with Itanium. Itanium's current Madison lineup is the same as it was at Madison launch: 1.3, 1.4 and 1.5Ghz speeds... That's what makes me think that it's somewhat likely that 2.5Ghz speeds will be available in 2H05.
reply:
Yes madison 1.6GHZ 3MB is release and 1.7GHz 9MB should be release real soon question of few month.Montecito 2.5 GHZ maybe the max speed it can reach on low power consumation with a overall clock speed lower.I expect more something like 2.2 GHZ unless they want to go over 130 max power consumation.
You assume, of course, that they did nothing to change that Xeon - I2 clock correspondence in hardware. However, they'd be wise to enhance 32-bit code execution... Even so, well, a Xeon MP with 24MB of cache and 10GB/s FSB would be nice at 2.5Ghz. And the other systemwide improvements will probably also make a difference in execution of 32-bit code.
Reply: why try to improve it it a big lose of time.
Hm, a 10.6GB/s isn't three times the bandwidth, so I assume the memory controller has been greatly enhanced and has been made much, much more efficient. Bear in mind that 10.6GB/s is either Dual DDR2-667 (which will be out by then, and possibly with better-than-standard timings) or quad-channel DDR333. Intel has been using quad DDR200/266 for Itanium up until now. I wouldn't be too surprised if at some point they went dual DDR2-667, if they want to promote socket compatibilities for Xeon/Itanium... <wild speculation>I wonder if all of a sudden Itanium had an on-die memory controller? For dual DDR2-667 or quad DDR333? </wild speculation>
Reply: 3 time the bandwith is easy math.
4 itanium share 6.4 GB\s (HP and SGI use only 2 cpu per FSB)
So if Montecito have a point to point bus with a legacy mode running at 166 MGHZ it got 3 time the performance.While in the same time compare to Altix per core there only a about 40% increase in bandwith.
The others possibility is the intel exec have make a mistake.
HP and SGI use Quad channel of DDR 266.They would just need to move to DDR 333.
That's for sure. IA64 with 24MB of cache, 2.5Ghz? I don't think even any IBM server-class processor will match that easily at all. I think it was P4Man who said that IBM's Power5 @ 1.9Ghz (current existing dual-core design) would not be outclassed by Montecito? Well, enter dual 2.5Ghz Itanium cores, and things ought to change a little...
Reply:
Power 5 wont stand a single chance maybe Power 5+ at 3 ghz.
i need to change useur name.
reply:
Yes madison 1.6GHZ 3MB is release and 1.7GHz 9MB should be release real soon question of few month.Montecito 2.5 GHZ maybe the max speed it can reach on low power consumation with a overall clock speed lower.I expect more something like 2.2 GHZ unless they want to go over 130 max power consumation.
You assume, of course, that they did nothing to change that Xeon - I2 clock correspondence in hardware. However, they'd be wise to enhance 32-bit code execution... Even so, well, a Xeon MP with 24MB of cache and 10GB/s FSB would be nice at 2.5Ghz. And the other systemwide improvements will probably also make a difference in execution of 32-bit code.
Reply: why try to improve it it a big lose of time.
Hm, a 10.6GB/s isn't three times the bandwidth, so I assume the memory controller has been greatly enhanced and has been made much, much more efficient. Bear in mind that 10.6GB/s is either Dual DDR2-667 (which will be out by then, and possibly with better-than-standard timings) or quad-channel DDR333. Intel has been using quad DDR200/266 for Itanium up until now. I wouldn't be too surprised if at some point they went dual DDR2-667, if they want to promote socket compatibilities for Xeon/Itanium... <wild speculation>I wonder if all of a sudden Itanium had an on-die memory controller? For dual DDR2-667 or quad DDR333? </wild speculation>
Reply: 3 time the bandwith is easy math.
4 itanium share 6.4 GB\s (HP and SGI use only 2 cpu per FSB)
So if Montecito have a point to point bus with a legacy mode running at 166 MGHZ it got 3 time the performance.While in the same time compare to Altix per core there only a about 40% increase in bandwith.
The others possibility is the intel exec have make a mistake.
HP and SGI use Quad channel of DDR 266.They would just need to move to DDR 333.
That's for sure. IA64 with 24MB of cache, 2.5Ghz? I don't think even any IBM server-class processor will match that easily at all. I think it was P4Man who said that IBM's Power5 @ 1.9Ghz (current existing dual-core design) would not be outclassed by Montecito? Well, enter dual 2.5Ghz Itanium cores, and things ought to change a little...
Reply:
Power 5 wont stand a single chance maybe Power 5+ at 3 ghz.
i need to change useur name.
Mephistopheles
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The Madison 1.6Ghz, 3MB cache version is a dual-processor only and is not intended as a highest-end processor; the highest-end Madison is still the good old 1.5Ghz processor. A good indication of that is that the 1.5Ghz still stands quite solidly at its "ultra-high" price niche (~$4200), and the 1.6Ghz is cheaper.
And the Madison 9M is actually a core revision in itself... From what I've heard, it's almost as if it's a new core version, like going from McKinley to Madison.
It would be a new thing if Intel released Montecito as a 2.2Ghz, then introduced 2.3, 2.4 and 2.5Ghz versions. What they usually do is introduce a whole family, and they don't go speed bumping until the next core, which gives way to another spectrum of frequencies.
Like Banias. Banias came at 1.4, 1.5, 1.6 and 1.7Ghz flavours, right from the start. It took Dothan to go above the initial 1.7Ghz, they did not speed bump.
Mephistopheles
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BTW...
Going point-to-point in quad-processor systems would help them immensely; in theory, they could say they've increased bandwidth a lot: from 6.4GB/s to a staggering 42.4GB/s. Impressive.
If indeed Montecito is such a great improvement over its predecessors, Intel should send out a handful of these systems (dual or quad-processor based; 4 our 8 core-based; 8 or 16 thread capable) for review by hardcore enthusiast sites. These things could make a point for themselves easily, if they're indeed technically strong as the specs suggest.
No, it's not. If Itanium did a better job at generic 32-bit code, its acceptance might be speeded up considerably.
Hm, you're right here... it is conceivable that they're considering point-to-point busses. 6.4GB/s for two-cpu systems would be upgraded to twice 10.6GB/s, which is 21.2GB/s, which is, of course, around 3*6.4=19.2GB/s. Not bad.
Going point-to-point in quad-processor systems would help them immensely; in theory, they could say they've increased bandwidth a lot: from 6.4GB/s to a staggering 42.4GB/s. Impressive.
If indeed Montecito is such a great improvement over its predecessors, Intel should send out a handful of these systems (dual or quad-processor based; 4 our 8 core-based; 8 or 16 thread capable) for review by hardcore enthusiast sites. These things could make a point for themselves easily, if they're indeed technically strong as the specs suggest.
No, it's not. If Itanium did a better job at generic 32-bit code, its acceptance might be speeded up considerably.
reply:
Acception in desktop workstastion it not possible as it will still need driver OS and higher clock speed.
Hm, you're right here... it is conceivable that they're considering point-to-point busses. 6.4GB/s for two-cpu systems would be upgraded to twice 10.6GB/s, which is 21.2GB/s, which is, of course, around 3*6.4=19.2GB/s. Not bad.
Going point-to-point in quad-processor systems would help them immensely; in theory, they could say they've increased bandwidth a lot: from 6.4GB/s to a staggering 42.4GB/s. Impressive.
If indeed Montecito is such a great improvement over its predecessors, Intel should send out a handful of these systems (dual or quad-processor based; 4 our 8 core-based; 8 or 16 thread capable) for review by hardcore enthusiast sites. These things could make a point for themselves easily, if they're indeed technically strong as the specs suggest.
reply:
The best part is the number of hop will decrease by half so the worst latency in large systemes will decrease by a large factor Opteron and EV7 in large SSI 128 way and more is plague with very high worst snenario latency much worst that itanium.A 64 way Superdome or Altix or summit have 2 or 4 CPU per cell and each are attach to the fabric.
A cell of montecito will have 2 CPU and 4 core per cell.Before you choice was either 1.6GBS with 16 cell or 3.2GBS with 32 cell.Now with montecito you have 5 GBS on 16 cell.Only hick is the bandwith stress on the fabric a single cell now have twice as much CPU that are twice as fast so in short 4 time the computing power in the same cell so the need for bandwith from this point will be much higher.SGI have change there fabric from NL3 to NL4 having twice the bandwith but others will have to make,buy or license a faster fabric.Chipset will have to be develope as the new itanium chipset from intel been cancel.HP SGI IBM will have no probleme with this but smaller corp that dont have the resource will be force to drop itanium or license it from HP or else and last option is to use E8870 that will offer much slower performance and support only 400 FSB.<P ID="edit"><FONT SIZE=-1><EM>Edited by juin on 08/16/04 11:55 AM.</EM></FONT></P>
reply:
Acception in desktop workstastion it not possible as it will still need driver OS and higher clock speed.
Hm, you're right here... it is conceivable that they're considering point-to-point busses. 6.4GB/s for two-cpu systems would be upgraded to twice 10.6GB/s, which is 21.2GB/s, which is, of course, around 3*6.4=19.2GB/s. Not bad.
Going point-to-point in quad-processor systems would help them immensely; in theory, they could say they've increased bandwidth a lot: from 6.4GB/s to a staggering 42.4GB/s. Impressive.
If indeed Montecito is such a great improvement over its predecessors, Intel should send out a handful of these systems (dual or quad-processor based; 4 our 8 core-based; 8 or 16 thread capable) for review by hardcore enthusiast sites. These things could make a point for themselves easily, if they're indeed technically strong as the specs suggest.
reply:
The best part is the number of hop will decrease by half so the worst latency in large systemes will decrease by a large factor Opteron and EV7 in large SSI 128 way and more is plague with very high worst snenario latency much worst that itanium.A 64 way Superdome or Altix or summit have 2 or 4 CPU per cell and each are attach to the fabric.
A cell of montecito will have 2 CPU and 4 core per cell.Before you choice was either 1.6GBS with 16 cell or 3.2GBS with 32 cell.Now with montecito you have 5 GBS on 16 cell.Only hick is the bandwith stress on the fabric a single cell now have twice as much CPU that are twice as fast so in short 4 time the computing power in the same cell so the need for bandwith from this point will be much higher.SGI have change there fabric from NL3 to NL4 having twice the bandwith but others will have to make,buy or license a faster fabric.Chipset will have to be develope as the new itanium chipset from intel been cancel.HP SGI IBM will have no probleme with this but smaller corp that dont have the resource will be force to drop itanium or license it from HP or else and last option is to use E8870 that will offer much slower performance and support only 400 FSB.<P ID="edit"><FONT SIZE=-1><EM>Edited by juin on 08/16/04 11:55 AM.</EM></FONT></P>
>Very interesting news on montecito. I was expecting it to
>be roughly a 2Ghz part, but it seems 2.5Ghz is definitely
>over-the-top powerful
Nah, keep in mind server cpu's like Power and Itanium don't come in as many flavours or speedgrades as our desktop chips where we are used to new speedgrades every few months. So if a new server chip comes out, its likely king of the hill (or at least, king of its own private little hill
for a while. When Itanium2 came out, it leapfrogged Power and x86, but meanwhile Power5 has convincingly regained the performance crown, and x86 has closed to gap considerably (not too say its in fact faster for quite a few things). I expect something similar to happen with Montecito, it may well be the fastest chip when it comes out, but it won't take long for x86/Power5+/6 to catch it again. Over and over, rince, repeat,.. heck, even Sparc64 is looking pretty damn impressive on paper these days. Also keep in mind a couple of percent performance is worth nothing in these markets (except HPC). No one will migrate to another architecture if performance or priceperformance isn't at least a factor 2 better. If not, Sparc wouldn't still be the best selling non x86 architecture out there.. So if you are a new kid on the block and want to capture marketshare from the established ISA's, you'd better be by far the fastest..
As for better x86 performance.. I'm not sure how crucial it is. For workstations it would be a considerable asset no doubt, but no one likes running critical non native code on a server, even regardless of performance. Servers also typically run a very limited ammount of apps, so either those are available natively, or you wouldn't consider the architecture for that app. Its nice once in a while perhaps to be able to use old tools or some odd ugly legacy code you don't want to touch, but those are probably not performance sensitive.
= The views stated herein are my personal views, and not necessarily the views of my wife. =
>be roughly a 2Ghz part, but it seems 2.5Ghz is definitely
>over-the-top powerful
Nah, keep in mind server cpu's like Power and Itanium don't come in as many flavours or speedgrades as our desktop chips where we are used to new speedgrades every few months. So if a new server chip comes out, its likely king of the hill (or at least, king of its own private little hill
for a while. When Itanium2 came out, it leapfrogged Power and x86, but meanwhile Power5 has convincingly regained the performance crown, and x86 has closed to gap considerably (not too say its in fact faster for quite a few things). I expect something similar to happen with Montecito, it may well be the fastest chip when it comes out, but it won't take long for x86/Power5+/6 to catch it again. Over and over, rince, repeat,.. heck, even Sparc64 is looking pretty damn impressive on paper these days. Also keep in mind a couple of percent performance is worth nothing in these markets (except HPC). No one will migrate to another architecture if performance or priceperformance isn't at least a factor 2 better. If not, Sparc wouldn't still be the best selling non x86 architecture out there.. So if you are a new kid on the block and want to capture marketshare from the established ISA's, you'd better be by far the fastest..As for better x86 performance.. I'm not sure how crucial it is. For workstations it would be a considerable asset no doubt, but no one likes running critical non native code on a server, even regardless of performance. Servers also typically run a very limited ammount of apps, so either those are available natively, or you wouldn't consider the architecture for that app. Its nice once in a while perhaps to be able to use old tools or some odd ugly legacy code you don't want to touch, but those are probably not performance sensitive.
= The views stated herein are my personal views, and not necessarily the views of my wife. =
Mephistopheles
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You're right about that; servers often use only a few apps (heck, 1 or 2 quickly enough, and it's good enough), but I meant to increase Itanium's general attractiveness to the workstation and scientific community (of which I am part of)... This niche needs to constantly write or rewrite code... And is quite demanding in terms of floating-point performance!
I think there would be quite a few reasons to somewhat enhance Itanium's 32-bit execution engine... Firstly, consider that they might be planning a socket compatibility with Xeon. This in itself should warrant an improvement in 32-bit app execution; you're not going to shell out $4000+ for an Itanium processor to fit in a socket in which you could put a, say, $400 Xeon and get better 32-bit support, unless you truly want that one single native app to run faster on IA64. Even if they don't change anything in hardware, though, the emulation layer has been under development for a while, and a 2.5Ghz Montecito without more 32-bit support will be quite a bit faster than the current Madison core at conventional and non-specific code.
Which brings me to an interesting question: will itanium be able, in the future, to process EM64T code? If so, <b>can the x86-64 instructions be mapped with IA64 code in such a way that an Itanium might come to execute, possibly through software emulation, EM64T code <i>faster</i> than a Xeon?...</b> Assuming, for a second, that there is no hardware change specifically designed to accomodate EM64T instructions (like the inclusion of dedicated 32-bit/64-bit EM64T-like circuitry)...
(it could be a dumb question, but I had to try... I don't know nearly enough about IA64 and x86-64 extensions to compare them. It would make x86-64 code deployment work for increased Itanium migration... I'd expect someone at Intel to have thought about this at some point... I'd imagine it would also take a lot of knowledge about IA64's ISA and its potential to answer this question properly... If anyone could provide me with an introductory link on IA64, that would be helpful... I'll look for it myself, but if anyone by any chance has anything, I'd appreciate some help very much.
)
Mephistopheles
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Although, I was thinking, this is absurdly speculative... Heck, we don't have a lot of performance benchmarks on A64 technology with 64-bit support (not for the vast majority of performance-demanding apps, anyway); we have no idea as to Nocona's 64-bit performance, and we don't know anything about pretty much anything... :frown:
Windows for 64-bit extended systems isn't out, so whatever...
Windows for 64-bit extended systems isn't out, so whatever...
> Firstly, consider that they might be planning a socket
>compatibility with Xeon
No need to say 'might', they are planning this.. well, intel didn't specifically say "socket compatible" but "platform compatible" (or "system" or whatever they called), meaning at least on the chipset side of things, but most likely sockets as well.
>you're not going to shell out $4000+ for an Itanium
>processor to fit in a socket in which you could put a, say,
>$400 Xeon and get better 32-bit support
First, Itanium CPU's aren't that much more expensive as Xeons, if you compare apples to apples (in so much that is possible). 1.4/3M Itaniums list around $1500 if I'm not mistaken, and Xeon MP with big caches aren't any cheaper. Secondly, intel promised twice the performance/$ over Xeon within a couple of years. Whatever that means (only FP ? or are they going to double Xeon prices. Finally, for certain specific apps, Itanium may well be more cost effective already, in spite of the expensive platform..
>Which brings me to an interesting question: will itanium be
>able, in the future, to process EM64T code?
Hmm.. it shouldn't be much harder as executing x86. However, I doubt it will be done in hardware, from what I read, I got the impression intel was going to abandon binary x86 compatibility in hardware all together and rely on software emulation. It shouldn't be too difficult to adapt that software to run AMD64 code as well .
>an the x86-64 instructions be mapped with IA64 code in such
>a way that an Itanium might come to execute, possibly
>through software emulation, EM64T code faster than a Xeon?
Maybe, maybe not. I thought current software emulation already vastly outperformed to sucky hardware x86, giving roughly 40% of the speed of native IA64 code (which is *very* respectable). Now if Itanium performance increases by leaps and bounds, and x86 stands virtually still by comparison, the answer to your question will be a "yes".
Still, software emulation ain't perfect; performance can varry greatly, and compatibility is far from perfect. Further more, it is not trusted. Lastly, I don't really see the big benefit for intel. They are trying everything to make people port to IA64, and they are donig what they can to slow down AMD64. I just don't see the benefit of adding AMD64 compatibility to IA, there is more (relevant) IA64 software than AMD64... I'd rather see intel try the opposite (let xeons execute IA64) however unlikely and nearly impossible that would seem to me.
= The views stated herein are my personal views, and not necessarily the views of my wife. =
>compatibility with Xeon
No need to say 'might', they are planning this.. well, intel didn't specifically say "socket compatible" but "platform compatible" (or "system" or whatever they called), meaning at least on the chipset side of things, but most likely sockets as well.
>you're not going to shell out $4000+ for an Itanium
>processor to fit in a socket in which you could put a, say,
>$400 Xeon and get better 32-bit support
First, Itanium CPU's aren't that much more expensive as Xeons, if you compare apples to apples (in so much that is possible). 1.4/3M Itaniums list around $1500 if I'm not mistaken, and Xeon MP with big caches aren't any cheaper. Secondly, intel promised twice the performance/$ over Xeon within a couple of years. Whatever that means (only FP ? or are they going to double Xeon prices
. Finally, for certain specific apps, Itanium may well be more cost effective already, in spite of the expensive platform..>Which brings me to an interesting question: will itanium be
>able, in the future, to process EM64T code?
Hmm.. it shouldn't be much harder as executing x86. However, I doubt it will be done in hardware, from what I read, I got the impression intel was going to abandon binary x86 compatibility in hardware all together and rely on software emulation. It shouldn't be too difficult to adapt that software to run AMD64 code as well .
>an the x86-64 instructions be mapped with IA64 code in such
>a way that an Itanium might come to execute, possibly
>through software emulation, EM64T code faster than a Xeon?
Maybe, maybe not. I thought current software emulation already vastly outperformed to sucky hardware x86, giving roughly 40% of the speed of native IA64 code (which is *very* respectable). Now if Itanium performance increases by leaps and bounds, and x86 stands virtually still by comparison, the answer to your question will be a "yes".
Still, software emulation ain't perfect; performance can varry greatly, and compatibility is far from perfect. Further more, it is not trusted. Lastly, I don't really see the big benefit for intel. They are trying everything to make people port to IA64, and they are donig what they can to slow down AMD64. I just don't see the benefit of adding AMD64 compatibility to IA, there is more (relevant) IA64 software than AMD64... I'd rather see intel try the opposite (let xeons execute IA64) however unlikely and nearly impossible that would seem to me.
= The views stated herein are my personal views, and not necessarily the views of my wife. =
Mephistopheles
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Well, in either case, I'll be keeping a close eye on Montecito.
After all, it will be the culmination of two years of Intel's research, as Madison is already quite an old architecture. And Madison 9M isn't quite a new core at all, I've read a little more on the subject.
Montecito was originally slated for 2004, but wasn't dual core. It was, however, designed for 2+Ghz speeds, with some speculating that Montecito would eventually reach 3Ghz. Seems far-fetched, but I've seen a few links on the net that point to that speed. It would be hard to keep up such a gargantuan speed gain with dual-core, but Montecito should in any case be considerably superior, core-for-core, than Madison, that's for sure. Not only in clock, but also in features - montecito is <i>not</i> based on two Madison 9M cores crammed together with more cache. It's much more sophisticated than that. And hopefully, if Intel isn't being run by apes (no, no betting on the fact that it is, please ), then the Alpha team and the <A HREF="http://www.xbitlabs.com/news/cpu/display/20040525031730.html" target="_new">Elbrus research</A> should pay off at some point!)
So, while Madison and its 9M big brother are rather dull from today's point of view, Montecito could still stir up things a little. (after all, Intel's 32-bit plans seem completely shattered by the netburst design suicide)
BTW, why do they need such ridiculously high amounts of cache? To keep all execution units properly fed? Or can't they perfect memory access through less expensive, smarter ways? (well, at least conventional memory can't possibly give them the 48GB/s bandwidth that the current L3 caches on Madison have... Sharing the 50+GB/s the 24MB L3 on Montecito will offer will probably be no problem, and sharing would probably add much to the overall speed. Heck, each core would have access to a 24MB cache at several dozen gigabytes a second?)
<i>Edit: Here's <A HREF="http://www.xbitlabs.com/news/cpu/display/20040619180753.html" target="_new">the link</A> for the montecito demo (well, OK, they just showcased a silicon wafer with it) dating back from June, the 19th. So it would seem Intel has silicon for Montecito ready a whole year before its launch...</i><P ID="edit"><FONT SIZE=-1><EM>Edited by Mephistopheles on 08/16/04 10:27 PM.</EM></FONT></P>
After all, it will be the culmination of two years of Intel's research, as Madison is already quite an old architecture. And Madison 9M isn't quite a new core at all, I've read a little more on the subject.
Montecito was originally slated for 2004, but wasn't dual core. It was, however, designed for 2+Ghz speeds, with some speculating that Montecito would eventually reach 3Ghz. Seems far-fetched, but I've seen a few links on the net that point to that speed. It would be hard to keep up such a gargantuan speed gain with dual-core, but Montecito should in any case be considerably superior, core-for-core, than Madison, that's for sure. Not only in clock, but also in features - montecito is <i>not</i> based on two Madison 9M cores crammed together with more cache. It's much more sophisticated than that. And hopefully, if Intel isn't being run by apes (no, no betting on the fact that it is, please
), then the Alpha team and the <A HREF="http://www.xbitlabs.com/news/cpu/display/20040525031730.html" target="_new">Elbrus research</A> should pay off at some point!)So, while Madison and its 9M big brother are rather dull from today's point of view, Montecito could still stir up things a little. (after all, Intel's 32-bit plans seem completely shattered by the netburst design suicide)
BTW, why do they need such ridiculously high amounts of cache? To keep all execution units properly fed? Or can't they perfect memory access through less expensive, smarter ways? (well, at least conventional memory can't possibly give them the 48GB/s bandwidth that the current L3 caches on Madison have... Sharing the 50+GB/s the 24MB L3 on Montecito will offer will probably be no problem, and sharing would probably add much to the overall speed. Heck, each core would have access to a 24MB cache at several dozen gigabytes a second?)
<i>Edit: Here's <A HREF="http://www.xbitlabs.com/news/cpu/display/20040619180753.html" target="_new">the link</A> for the montecito demo (well, OK, they just showcased a silicon wafer with it) dating back from June, the 19th. So it would seem Intel has silicon for Montecito ready a whole year before its launch...</i><P ID="edit"><FONT SIZE=-1><EM>Edited by Mephistopheles on 08/16/04 10:27 PM.</EM></FONT></P>
Mephistopheles
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Are they really that early or is it expected to have silicon for a server chip 12+ months before it gets launched?
Could they play this card sooner than expected, if truly needed?...
Could they play this card sooner than expected, if truly needed?...
>Are they really that early or is it expected to have
>silicon for a server chip 12+ months before it gets
>launched?
12 months lead time sounds about right for a new core. Remember Pat Gelsinger help up a Montecito wafer at IDF. I'm sure those dies have been sliced and packaged by now
= The views stated herein are my personal views, and not necessarily the views of my wife. =
>silicon for a server chip 12+ months before it gets
>launched?
12 months lead time sounds about right for a new core. Remember Pat Gelsinger help up a Montecito wafer at IDF. I'm sure those dies have been sliced and packaged by now
= The views stated herein are my personal views, and not necessarily the views of my wife. =
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