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Why is my front side bus showing as 200MHZ?

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November 21, 2004 7:02:35 PM

I just put together a new PC with the following specs:

Asus P4P800-SE motherboard
Intel P4 3.0 w/ HT (Prescott)
1 GB of dual-channel RAM

Everything is fast so far but in all my benchmark and system info utilities, it is showing 200mhz front side bus. The motherboard supports 800mhz FSB and so does the P4 chip. It also shows 800 in the bios. Why is windows showing 1/4 of that?

Thanks for the help.
November 21, 2004 7:03:46 PM

Because your PC3200 mem runs at 200mhz, quad pumped or x4 = 800mhz

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November 21, 2004 7:48:41 PM

Its not anything to do with his memory, he doesnt have to have dual channel memory or PC3200 to have a FSB of 800Mhz. Nowadays the FSB relates to the speed the northbridge connects to CPU and has nothing to do with memory.

The pentium4C and E use a 200Mhz FSB but this has 4piplines giving an effective data rate of 6.4GB/sec (which can be considered 800Mhz). So your system is working correctly. They say it is 800Mhz rather than 4x200 because it sounds better.

The best memory configuration to use with this is 2 or 4 sticks or PC3200. PC3200 runs at 200Mhz but sends signals on the rising and falling edge of a voltage spike, effectivly making it work at 400Mhz. By using two sticks it enables dual channel mode (combining two 64bit buses into a single 128bit bus), thus doubling the bandwidth again giving you 6.4GB/sec of bandwidth...matching the P4's FSB perfectly.
November 21, 2004 8:13:19 PM

Quote:
The pentium4C and E use a 200Mhz FSB but this has 4piplines giving an effective data rate of 6.4GB/sec (which can be considered 800Mhz). So your system is working correctly. They say it is 800Mhz rather than 4x200 because it sounds better.



I didtn know you could get more than dual channel yet

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November 21, 2004 8:27:17 PM

[stupidity]The p4 use a quad pumped super pipe line with 4mb of intergrated cache wich result into a a 4x4 total pipeline FSB (Face Subtitute Bullshit). 4x4=16 , 16x12.5 (Cpu multiplier) = 200mhz x 4 = 800mhz. [/stupidity]

Woot.

Signature (up to 200 characters). You may use <font color=blue><b>Markup</b></font color=blue> in your signature<P ID="edit"><FONT SIZE=-1><EM>Edited by coylter on 11/21/04 06:35 PM.</EM></FONT></P>
November 21, 2004 9:03:24 PM

? I didnt say you could?
November 21, 2004 11:08:38 PM

Well see this is what I have been trying to work out, DDR works by sending data on the rising and falling edge of each voltage spike. Hell the hell does QDR work? You cant send 4 signals on the rising and falling edge of a clock cycle. So I assumed it was using 4buses (dunno why I called them piplines)..or perhaps 2 DDR buses?

Anyone want to shed any light on this?
November 21, 2004 11:09:27 PM

Quote:
The p4 use a quad pumped super pipe line with 4mb of intergrated cache wich result into a a 4x4 total pipeline FSB


Where is the 4mb cache located?

<font color=red><pre>\\//__________________________________
And the sign says "You got to have a membership card to get inside" Huh
So I got me a pen and paper And I made up my own little sign</pre><p></font color=red>
November 21, 2004 11:40:21 PM

<A HREF="http://sysopt.earthweb.com/articles/qdr-sram/index3.htm..." target="_new">http://sysopt.earthweb.com/articles/qdr-sram/index3.htm...;/A>

<A HREF="http://www.altera.com/literature/an/an349.pdf" target="_new">http://www.altera.com/literature/an/an349.pdf&lt;/A>


think of it as a radio wave. the clock generator creates a pulse or wave that rises and falls. sdr memory kept its timing by keeping sync with the rising edge of teh signal, ddr used the rising and falling edge, and qdr uses the rising and falling edge twice each. im probably saying it wrong, because i dont know that much , but its pretty close i guess.

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November 22, 2004 1:43:30 AM

[stupidity]DUDE its a quad pumped 1 mb cache...DUH[/stupidity]

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a b à CPUs
November 22, 2004 4:47:29 AM

OK, now that you've heard some BS and guesses, let me tell you the truth that so many informed members haven't bothered with (probably because the question gets asked too much):

The Pentium 4 800 bus is actually 200MHz. That's a clock speed. It has a 4x data rate using Quad Data Rate technology. This is similar to the technology used to make the AGP4x bus "4x". It means that 4 chunks of data are sent every clock cycle, rather than one. Hence "Quad Data Rate" means the data rate is 4 times (Quad) the clock speed.

Now, the proper memory for that would be Double Data Rate 400 (200MHz clock x2). Since DDR400 has the same clock speed but 1/2 the data multiplication factor of the CPU bus, Dual Channel configuration is the solution to making it provide the same bandwidth.

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November 22, 2004 5:12:25 AM

There are no pumps, it's the data rate thats increased, that's why it's called Quad Data Rate.

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November 22, 2004 6:35:33 AM

4 pipelines? LMAO! The closest thing to that is the <b>64 data paths</b> of it's front side bus! Not 4, 64.

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November 22, 2004 10:16:25 AM

Thanks Phial, the second link was quite helpfull. The way I understand it QDR is exactly the same as DDR (in that is sends Data on the rising and falling edge of each clock cycle). Except QDR uses 2 unidirectional data buses, one for reads and one for writes.

Im not sure if the pentium4 bus work the same way as QDR RAM though, because I was always under the impression the P4 bus was half duplex(it cant send data in both directions at the same time).
November 22, 2004 11:12:05 AM

You just copied me, you learn well grasshopper! :) 

<font color=red><pre>\\//__________________________________
And the sign says "You got to have a membership card to get inside" Huh
So I got me a pen and paper And I made up my own little sign</pre><p></font color=red>
November 22, 2004 11:25:55 AM

No he didnt, you were talking about memory speeds!
November 23, 2004 1:20:58 AM

I remember a cheerleader in a '64 Oldsmobile with four football players on a Friday night. I guess you could say she was "quad-pumped". :lol: 


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