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Intel's New Architecture + IDF stuff...

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Anonymous
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August 23, 2005 5:38:17 PM

Some details are starting to appear!
<A HREF="http://www.anandtech.com/tradeshows/showdoc.aspx?i=2504" target="_new">Anand's got a small page with some details</A>

Not the completly new architecture some people where speculating. Its the more obvious NetBurst - P-M merge.

Most interesting facts: 4-issue wide core, 14 stages pipeline, and also some sort of direct L1 to L1 cache transfer(between the 2 cores).

Seams promising, and now we understand Apple's move a little better, specialy when they where talking about the "better performance per whatt" than the PPC...

We need more details now!!!

Asus P4P800DX, P4C 2.6ghz@3.25ghz, 2X512 OCZ PC4000 3-4-4-8, MSI 6800Ultra stock, 2X30gig Raid0<P ID="edit"><FONT SIZE=-1><EM>Edited by labbbby on 08/25/05 01:58 PM.</EM></FONT></P>
Anonymous
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August 23, 2005 5:47:40 PM

Also Fromt <A HREF="http://www.theinquirer.net/?article=25623" target="_new">TheInq</A>

Some more details.

Quote:
In addition, Merom has Macro-Op fusion, the ability to gang x86 operations before decode. As an example, if you have a multiply followed by an add, Macro-Op fusion can turn that into a Multiply and Accumulate. Again, this simplifies the complex process of x86 execution and again increases IPC.

Quote:
Merom goes well beyond this, all units are powered down in the default state. When units are needed , they are powered up, and the chip takes power savings to a new level entirely. The unit power up takes a few clock cycles, and again, while exact numbers are classified, it is more than one, less than 10 in most cases. This depends greatly on processor power state, but it should not be all that noticable.

Quote:
A lot of this is due to bandwith to the cores, and that is the weakest link for Merom. They keep the current infrastructure, can keep the chipsets, and keep the FSB. The target for Woodcrest, the server version of Merom is a 1333MHz FSB. The quad core MCM Clovertown will drop down to 1066, and Conroe will sit on 1066 also. I think that Conroe will end up on a 1333, but officially, it isn't. Merom will be lower due to power constraints.


Finally TDP of 65W @ 2.5-3ghz!

Sounds really good to me!

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August 24, 2005 3:13:55 PM

It's IDF, so <i>everyone</i> has tons of Intel 'news' (IE. marketing rehash) right now.

But still, some of it does look interesting. For example, <A HREF="http://www.theregister.co.uk/2005/08/23/intel_soi_vs_st..." target="_new">Intel still refuses to use SOI</A>. So how well will they do against AMD on power use then? That should be fairly interesting to see.

We also see that Intel finally got <A HREF="http://www.theregister.co.uk/2005/08/23/intel_fixes_em6..." target="_new">the updated AMD64 documents from AMD</A>. Sorry to all of you early EM64T adopters. With Intel now doing it right, your flawed version is going to overlooked by many software developers.

And here's some more <A HREF="http://www.theregister.co.uk/2005/08/23/intel_sossaman_..." target="_new">on Yonah and Sossaman</A>.

With all of the plans that Intel is making for the future now, I wonder what AMD is doing...

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Anonymous
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August 24, 2005 3:52:40 PM

Good point on AMD...Altoguht they have a good lead, I wonder whats up with K10(saw that K9 was skipped or considered DC of K8...not much info!)
K8 is suppose to remains for the whole 2006, I wonder what the future will bring us!

Another itneresting Tidbit on Conroe:
Quote:
* The design philosophy for the company's next-generation Pentium architecture -- which still lacks an official name -- is entirely new, Smith said. Although its inspiration was the cooler, more efficient Pentium M architecture developed by Intel's Israel Design Center, he said the new architecture is not directly derived from any previous project.
* Expect to see very modest performance gains over the lifetime of Merom/Conroe/Woodcrest. Speed is no longer key.
* Contrary to reports yesterday, hyperthreading is not dead, if you consider life support as "alive." The role of HT in Intel architectures going forward will be diminished somewhat. Expect to see HT as a feature of CPUs in the server space and high-end, said Smith, but certainly not for notebooks.
* L2 cache size may become the key distinguishing factor for raw performance going forth, said Smith. Yesterday, Intel CEO Paul Otellini, in his keynote address to IDF, characterizing the new "performance-per-watt"Ý figure would be the principal variable distinguishing the performance of future CPUs, replacing the traditional megahertz value. But Smith's comment today touting L2 size as the key factor, may indicate that Intel has yet to formalize a new "power scale"Ý strategy to replace megahertz. While Smith could not confirm the specific L2 cache size for Conroe processors, he did not deny the possibility of an 8 Mb L2 cache -- a figure previously reported in Tom's Hardware Guide as likely.

Expect to see very modest performance gains over the lifetime of Merom/Conroe/Woodcrest. Speed is no longer key.

Now what the Hell cant they provide both of them! SPeed and lower poer consumption! Its more than a 180 spin!


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August 24, 2005 4:16:09 PM

I'm just hoping For some 'new' Northwood A 1.6Ghz chips... :evil: 

Hopefully this will let intel put <i>that</i> core behind them, and produce something worth considering once more. Scotty Just so sucks - I wonder how many peeps out there have overheating/throttling systems without realising? (based on my buddy's Fujitsu, quite a few!)[/ok ok enough Intel-bashing!]

I would still like to see a 90nm Northwood core. Just curious what it would've been like...

I love this quote:
Quote:
Given the significant reduction in pipeline stages, Intel's claims of a 5x improvement in performance per watt over the Pentium 4 architecture seems very realistic.

Aaah! So <i>that's</i> why they made scotty suck so much juice - so they could look like they've made a huge improvement somewhere.... :evil: 

---
<font color=red>"Life is <i>not</i> like a box of chocolates. It's more like a jar of jalapeńos - what you do today might burn your a<b></b>ss tommorrow."
August 24, 2005 4:28:11 PM

Quote:
Good point on AMD...Altoguht they have a good lead, I wonder whats up with K10(saw that K9 was skipped or considered DC of K8...not much info!)
K8 is suppose to remains for the whole 2006, I wonder what the future will bring us!

I know. It seems like AMD has had so little information about their future. Hopefully they're just being secretive. Intel has been giving them a lot of breathing room so far. It'd be a shame if AMD wasted all of that opportunity like they did the last time they were doing this well.

Quote:
Now what the Hell cant they provide both of them! SPeed and lower poer consumption! Its more than a 180 spin!

I think the idea now is to design for IPC instead of clock. Cores may be defined more by their execution units. And CPUs may be defined more by the number of cores and the amount of cache shared between the cores.

It's all a very interesting approach to take ... so long as everyone and their brother codes multithreaded apps. Which, as a software developer, I just don't see happening.

I think if Intel (or anyone for that matter) wants this super-multi-cored concept to ever catch on, they're going to either need to work harder on instruction level parallelism, or they're going to need to find a way for multiple cores to work together on a single task. Because software developers just aren't that keen on multithreading their software if they can in any way avoid it. (And certainly some fair level of backwards compatability to old softwares should exist.)

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Anonymous
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August 24, 2005 4:29:19 PM

I jsut grabed a Willamette 1.6 socket 423 intersted!? hehe
no northwood thoguht...and its just sittign there...

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August 24, 2005 4:31:33 PM

Quote:
Aaah! So <i>that's</i> why they made scotty suck so much juice - so they could look like they've made a huge improvement somewhere.... :evil: 

**ROFL** Which is funny, because a "5x improvement in performance per watt" could mean that it uses 10x less power and performs half as well. :o  No one is saying that the <i>performance</i> is actually better.

Quote:
I would still like to see a 90nm Northwood core. Just curious what it would've been like...

Not just that, but a 90nm Northwood core with twice the cache and some of the same fixes that went into Scotty. Basically the logical upgrade to Northwood that should have been what Scotty was without the longer pipeline and other goofiness.

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@ 196K of 200K!<P ID="edit"><FONT SIZE=-1><EM>Edited by slvr_phoenix on 08/24/05 11:34 AM.</EM></FONT></P>
August 24, 2005 4:36:12 PM

Nah.. I just mean the 50% or more easy overclock with stock HSF..

So no, I don't particularly want a Willamette core.... :eek: 

---
<font color=red>"Life is <i>not</i> like a box of chocolates. It's more like a jar of jalapeńos - what you do today might burn your a<b></b>ss tommorrow."
August 24, 2005 4:38:32 PM

Quote:
and its just sittign there...

Not if you soak it in a solution of moth balls and petrol, strap it to a bundle of bottle rockets, and light the fuse. Now <i>that's</i> speeding up your CPU! :o 

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August 24, 2005 4:39:09 PM

Quote:
Basically the logical upgrade to Northwood that should have been what Scotty was without the longer pipeline and other goofiness.

Yup. They tried to cram too many fixes in, like a kid trying to make a sandwich containing <i>everything</i> they like :eek: 

---
<font color=red>"Life is <i>not</i> like a box of chocolates. It's more like a jar of jalapeńos - what you do today might burn your a<b></b>ss tommorrow."
Anonymous
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August 24, 2005 5:44:28 PM

LOL!
I'll post the Pics!

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August 24, 2005 5:53:50 PM

Quote:
Yup. They tried to cram too many fixes in

Really, the worst two 'fixes' were screwing around with the cache latencies and increasing the pipeline length to prepare Scotty to ramp several GHz higher. Without those two changes it would have been a good product.

Which is ironic, since the changes for a much higher clock speed were quickly rendered useless by the power inefficiencies. Scotty as it is has about the same clockspeed cap that it would have had if Intel hadn't screwred its performance to make it scale higher. :o  Oops.

Don't get me wrong. I can see where Intel thought the changes were a good idea. And <i>had</i> Scotty been able to scale up like Intel had expected it to, the changes would have been a smart move in the long run.

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August 24, 2005 5:57:20 PM

Quote:
LOL!
I'll post the Pics!

Could anyone even <i>not</i> post the pics after doing that? I mean you'd just <i>have</i> to. It'd be like winning the lotto and then not claiming the prize! :o 

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Anonymous
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August 24, 2005 6:05:46 PM

I see what you eman with the scotty. The best example is this CPU running a 7.2ghz benchable...All you need is minus 150-180 celcius for it to happen!


Lol @ the loto... I will find something creative dont worry. It has to do with "hot a 'n explosive" thought!


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August 25, 2005 5:18:24 AM

Quote:
90nm Northwood core with twice the cache

The extra cache is a big part of scotties problem. Not only are cache latencies a product of cache size, but the extra "on die" calls to cache have a major impact on heat.
I would prefer a 90nano northwood, with a 233 or 266 fsb.
Oh, wait a second, I'm an Amd fanbois, forgetaboutit.
August 25, 2005 12:44:51 PM

According to <A HREF="http://www.theregister.co.uk/2005/08/24/amd_quiet_idf" target="_new">this</A> it looks like the press can't drag anything more out of AMD's mouth than we can about what their future holds. :( 

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August 25, 2005 12:55:47 PM

Quote:
The extra cache is a big part of scotties problem. Not only are cache latencies a product of cache size, but the extra "on die" calls to cache have a major impact on heat.

Funny in the past, Intel and AMD have both managed to increase cache size without needing latencies as drastic as those in Scotty. My understanding was that the absurd latencies in Scotty were purely to help it scale several GHz higher. As for heat ... well, the leakage problem seems far more impacting than the extra cache is to me. Why Intel is so adamant against SOI is beyond me. I wonder if you could even combined strained silicon and SOI.

Quote:
I would prefer a 90nano northwood, with a 233 or 266 fsb.

No schiznit there! Memory keeps getting faster and faster.

Quote:
Oh, wait a second, I'm an Amd fanbois, forgetaboutit.

And, of course, if we wanted a CPU that performs well and doesn't run hot, instead of wondering about a better Northwood derivative, we'd just get a CPU from AMD. :o  (Though a new FSB from AMD would be nice too.)

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August 25, 2005 12:59:23 PM

Quote:
I doubt a faster Northwood will need more cache, but it would be nice to have 1MB just for that extra kick.

Da. I agree. Though when I think about it, I'm actually more concerned about doubling the L1 and all of the internal tables, queues, and such. That'd help HT work better. Theoreticly there's also doubling for EMT64 to consider as well, but meh. Who cares about x86-64?

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Anonymous
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August 25, 2005 5:58:07 PM

<A HREF="http://www.anandtech.com/tradeshows/showdoc.aspx?i=2511" target="_new">On-die North-bridge/voltage regulator/video</A>

Intersting, especially the on-die voltage regulator, that could save lots of power for mobile parts!

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August 25, 2005 7:18:53 PM

Quote:
Intersting, especially the on-die voltage regulator, that could save lots of power for mobile parts!

That's a very interesting showcase. Hopefully it's not too far away. :) 

Could you imagine if Intel did this in desktops too? There's be no more northbridges. Take that VIA. **ROFL** It'd sure be spiffy.

And I'm assuming that the integrated graphics can be disabled...

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Anonymous
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August 25, 2005 7:27:36 PM

Yup or why not make 2 version fo the chip? we have 2 version(or more) of the same northbridge to accomodate Integrated Graphx!

As for the No more NB, it did help ULI a lot with AMD(well remvoign the memory controller) because ALI use to have some issues with flakey mem controller, now their chipset should rock!

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August 25, 2005 7:46:52 PM

Quote:
Yup or why not make 2 version fo the chip? we have 2 version(or more) of the same northbridge to accomodate Integrated Graphx!

Yeah, but when it's the CPU that you're shipping, a version with the graphics and one without might be confusing. But then, I suppose it can't be any more confusing than what Intel is making things lately. :o 

Quote:
As for the No more NB, it did help ULI a lot with AMD(well remvoign the memory controller) because ALI use to have some issues with flakey mem controller, now their chipset should rock!

**ROFL** I never thought about it that way, but you make a good point. Though I think I'd have trusted nVidia to make the integrated mem controller a lot more than AMD just based on past chipsets. But hey, at least it's been working well so far. :)  So do these dinky 3rd party chipset manus see a significant stability boost from AMD taking the memory controller off of their hands? They probably see a performance boost at the very least...

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August 25, 2005 8:26:51 PM

<A HREF="http://www.computerbase.de/news/hardware/prozessoren/in..." target="_new">Sossaman and Yonah benchmarks.</A>

They need much higher clock speeds to keep up with AMD.

But then again, Intel is talking about performance/watt ratio, and not just about performance..

ps. look at the L2 latency, it's 15 cycles. IMO it's a bit high for P-M successor...
Or perhaps Intel is hiding something ?
(i posted that last comment so i wont look like AMD fanboy) :wink:

<font color=red>"We can't solve problems by using the same kind of thinking we used when we created them."
- Albert Einstein</font color=red><P ID="edit"><FONT SIZE=-1><EM>Edited by HansGruber on 08/25/05 11:32 PM.</EM></FONT></P>
August 26, 2005 2:25:06 PM

Quote:
ps. look at the L2 latency, it's 15 cycles. IMO it's a bit high for P-M successor...

I thought that the PMs were well known for having long L2 latencies because of their low power usage and the way that they can turn on and off sections of L2 to conserve power. Am I remembering this wrong? It's been a long time since I've actually read up on the PMs.

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Anonymous
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August 26, 2005 2:27:18 PM

UMmmm, wasnt one of the strenght of the P-m is large super low latency L2...
Same here Am I rembering wrong?

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!