> In the new Cedar Mill 65 nm process the strained silicon is
>improve by 15% which means less resistance and lower
>temperature.
The results arent really impressive, are they ? I cant remember a dieshrink ever only bringing a 20% power improvement per clock, and no increased clockspeeds at all. AFAIR even Tbred-A gained more from its shrink than Cedar Mill.
>Secondly, Intel has wisely kept the isolating layer between
> gates and electrodes the same as the 90 nm process at
>1.2nm. This means that components still maintain the same
>distance between each other. Clearly issues of thermal
>density are alleviated as the separation between
>components,
Rubbish. Thermal density as expressed in W/mm² has gone considerably up, not down. Yes, a heatspreader helps, but it wont stop the die from reaching higher temperatures than Prescott. Assume you'd have the same power consumption and same heatspreader area, but half the core size; what happens is that the heatsink and heatspreader will get equally hot, but the die temperature of the smaller core will be much higher. If you cant grasp that, consider how hot a 85W needle tip would be, or how hot it would have to be to heat up the heatsink as much a P4 does. Unless intel is now defnining TDPs differently as they did for Prescott, I guarantee you Cedar Mill will run hotter, and not just a tiny bit.
>personally feel that its a great start and that Intel
>should continue to increase clock speeds for Cedar Mill.
>Since the current motherboards support higher TDP, Intel
>might as well take advantage of it and scale speeds higher.
Its quite obvious they cant. 3.8 GHz Cedar Mill, even if it happens, seems to be a higher TDP part, most likely a review/PR sample that will hardly ship. And its not like 3.8 GHz prescotts where abundant. As it stands, 4.2 GHz is only a pipedream.
>Therefore increasing Cedar Mill to 4 GHz or 4.2 GHz will
>definitely yield increased performance per watt s
Thats the silliest thing I read in a while. Increasing clock speed increases power consumption proportionally if you can achieve it at the same Vcore. IRL, you usually need to increase Vcore to achieve higher clocks, which further increases power consumption, but this time, quadratically. Performance scales linear at best, but in reality, its almost always sublinear. So obviously increasing the clock *lowers* performance/watt. It always does.
>Intel develops the process of producing a chip at one
>fabrication plant. Once that process is finallized, the
>process is replicated exactly at all Intel's other
>fabrication plants. They use the same pressure, the same
>air, even the same water. Therefore, all chips will of the
>same performance. Nothing is "alarming" about that.
Non Sequitur. Endyens concern was that this sample was a cherry picked one. With any CMOS production you have good and bad samples. I dont share his concern as they didnt even measure temperatures so the only relevant information is the numbers (performance, TDP, die size which will apply for the entire line) , and further more this is a preproduction sample, so if anything, future products will likely be better, but your comments have nothing to do with this at all.
= The views stated herein are my personal views, and not necessarily the views of my wife. =
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