The P4 was a huge step backwards in IPC. Intel remade the PIII to a similar degree that AMD remade the Athlon, now we have Athlon 64's and Intel Pentium-M's with high IPC...and the P4 looks worse than ever.
<font color=blue>Only a place as big as the internet could be home to a hero as big as Crashman!</font color=blue>
<font color=red>Only a place as big as the internet could be home to an ego as large as Crashman's!</font color=red>
I'm not buying a P4 either. But I'm also not even looking at the P4 articles since their naming scheme makes it very annoying to read.
Eventually the OEM's will figure out what's going on and will start switching over to AMD.
You have to realize though that someone who keeps upgrading within the Intel family of processors is probably happy since to them they are getting an increase in performance. The problem is those that go from Intel to AMD and then try to go back to Intel. That's not fun.
<font color=red><b>Long live Dhanity and the minions scouring the depths of Wingdingium!</b>
XxxxX
(='.'=)
(" )_(" ) Bow down before King Bunny
yes, I have an AMD system for benchmarking, and I can't even use it because I need the parts for that purpose.
<font color=blue>Only a place as big as the internet could be home to a hero as big as Crashman!</font color=blue>
<font color=red>Only a place as big as the internet could be home to an ego as large as Crashman's!</font color=red>
Now you're just making me mad! [/true Intel fanboy]
Itanium and Itanium2 are still currently under development and won't be ready until 2007.
When IA matures it's going to pwn AMD so much that they don't know their arse has been surgically removed!
if by second class you mean making a ton more money then yes you are correct.
It doesn't bother if Intel makes zillion of dollars if they don't know how to use it the right way.
Just look at their roadmap: Delays, cancelled processors and the list keeps growing (don't even mention their actual offerings which are no competition to AMD's processors).
AMD being a smaller company knows how to spend money in a wise way.
What Intel is doing with all that money...
One has to wonder
My Beloved Rig:
ATHLON 64 FX 55 (will be changed for an X2 3800+)
2X1024 CORSAIR XMX XPERT MODULES
MSI K8N DIAMOND (SLI)
2 MSI 6800 ULTRA (SLI MODE)
OCZ POWERSTREAM 600W PSU<P ID="edit"><FONT SIZE=-1><EM>Edited by Bullshitter on 10/30/05 02:33 PM.</EM></FONT></P>
Just look at their roadmap: Delays, cancelled processors and the list keeps growing (don't even mention their actual offerings which are no competition to AMD's processors).
Isn't their roadmap merom, conroe and woodcrest? The only delays and whatnot are the crappy xeons and Itaniums.
Some people are like slinkies....
Not really good for anything but you cant help smile when you see one tumble down the stairs.
Well, Intel can blunder a lot without getting really hurt. They are that rich.
They have monopoly in CPU/Chip-set business globally and they think
they can fuckup in about anything without getting caught.
If in trouble, Intel drops a few GaZillions bucks more to the marketing dep, and pisses on the R&D dep, and orders for more champagne for their owners for making such a brilliant decision.
Intel’s roadmap actually isn’t too bad. While the delay of the integrated memory controller is a set back, it probably isn't as catastrophic as it appears.
Intel has been taking a lot of flak lately on their new Paxville DP. In this case, it is deserved. They decided to place 2 Prescott 620s together. The crazy heat production is directly due to the presence of not only HT in each processor but also an extra 1MB of L2 cache. Intel probably felt that the 1MB of extra cache per core was more worthwhile in a server environment than a 400MHz increase in clock rate, which is why they didn’t just use a 840EE. In the end, the 90nm process simply couldn’t handle dual core HT enabled processors with 2MB of cache per core. The lower performance compared to Opteron is due to the low clock speed of 2.8GHz and the bottleneck of 4 cores sharing a 800MHz FSB.
These problems will be greatly reduced once Dempsey and Bensley arrive. Dempsey will probably be closely related to Presler, meaning speeds of up to 3.46GHz HT enabled with 2MB of L2 cache per core. Higher clocked speeds are likely possible as a 3.4GHz 950 was shown to fit within the thermal and power envelop of a 2.8GHz 820. The higher clock speed will help, but the main benefit is the 1066MHz FSB. The 33.3% increase in bandwidth will satisfy Core-to-Core cache transfers while opening up more throughput to the RAM. Even more important is the addition of individual 1066MHz FSB pipes like what AMD has to ensure the processors don’t compete. In addition, the RAM speed has increased from 400MHz to 533MHz and is now quad-channelled. This means that total FSB bandwidth has nearly tripled from the 6.4GB/s in Paxville between 4 cores, to 17GB/s. Memory bandwidth has likewise tripled from 6.4GB/s to 17GB/s. Even a dual processor Opteron system only has 12.8GB/s of memory bandwidth available total. Dempsey and Bensley should certainly make Intel highly competitive with AMD.
Now to address the 4-way server market. While an integrated memory controller would provide better memory bandwidth scaling with additional processors, Intel’s current FSB architecture could easily be expanded to provide much of what’s required. Currently Intel’s Xeon MPs use a 667MHz FSB. Intel is already working on a 1333MHz FSB for Woodcrest, and the application of such a bus would double the available bandwidth. Of course, on the motherboard side, each processor would have an independent FSB to reduce congestion. Memory bandwidth would likewise see an increase from the current 400MHz to 667MHz in a quad-channel configuration. These improvements are easily made and will keep Intel competitive in the near-term.
One of the major improvements with the use of an integrated memory controller is the reduction in latency. The high latencies on Intel’s current systems is partially due to the memory running asynchronously with the FSB. This is corrected in Bensley where 533MHz RAM is matched with a 1066MHz FSB. By working synchronously, some of the latency issues will be reduced. Similary, Xeon MPs working with a 1333MHz FSB will run synchronously with 667MHz RAM. In addition, an advantage that Intel has over AMD is that they design their own chipsets. If they spent the effort, they could easily streamline the CPU-Northbridge-RAM interconnects to reduce latency.
All these are just simple improvements in the buses that will help improve Intel’s performance. Intel’s next-generation architecture isn’t even mentioned, but Conroe, Meron and Woodcrest are certainly something to look forward too. All in all, the delay of an integrated memory controller isn’t a catastrophe to Intel’s roadmaps.
Intel’s roadmap actually isn’t too bad. While the delay of the integrated memory controller is a set back, it probably isn't as catastrophic as it appears.
Intel has been taking a lot of flak lately on their new Paxville DP. In this case, it is deserved. They decided to place 2 Prescott 620s together. The crazy heat production is directly due to the presence of not only HT in each processor but also an extra 1MB of L2 cache. Intel probably felt that the 1MB of extra cache per core was more worthwhile in a server environment than a 400MHz increase in clock rate, which is why they didn’t just use a 840EE. In the end, the 90nm process simply couldn’t handle dual core HT enabled processors with 2MB of cache per core. The lower performance compared to Opteron is due to the low clock speed of 2.8GHz and the bottleneck of 4 cores sharing a 800MHz FSB.
These problems will be greatly reduced once Dempsey and Bensley arrive. Dempsey will probably be closely related to Presler, meaning speeds of up to 3.46GHz HT enabled with 2MB of L2 cache per core. Higher clocked speeds are likely possible as a 3.4GHz 950 was shown to fit within the thermal and power envelop of a 2.8GHz 820. The higher clock speed will help, but the main benefit is the 1066MHz FSB. The 33.3% increase in bandwidth will satisfy Core-to-Core cache transfers while opening up more throughput to the RAM. Even more important is the addition of individual 1066MHz FSB pipes like what AMD has to ensure the processors don’t compete. In addition, the RAM speed has increased from 400MHz to 533MHz and is now quad-channelled. This means that total FSB bandwidth has nearly tripled from the 6.4GB/s in Paxville between 4 cores, to 17GB/s. Memory bandwidth has likewise tripled from 6.4GB/s to 17GB/s. Even a dual processor Opteron system only has 12.8GB/s of memory bandwidth available total. Dempsey and Bensley should certainly make Intel highly competitive with AMD.
Now to address the 4-way server market. While an integrated memory controller would provide better memory bandwidth scaling with additional processors, Intel’s current FSB architecture could easily be expanded to provide much of what’s required. Currently Intel’s Xeon MPs use a 667MHz FSB. Intel is already working on a 1333MHz FSB for Woodcrest, and the application of such a bus would double the available bandwidth. Of course, on the motherboard side, each processor would have an independent FSB to reduce congestion. Memory bandwidth would likewise see an increase from the current 400MHz to 667MHz in a quad-channel configuration. These improvements are easily made and will keep Intel competitive in the near-term.
One of the major improvements with the use of an integrated memory controller is the reduction in latency. The high latencies on Intel’s current systems is partially due to the memory running asynchronously with the FSB. This is corrected in Bensley where 533MHz RAM is matched with a 1066MHz FSB. By working synchronously, some of the latency issues will be reduced. Similary, Xeon MPs working with a 1333MHz FSB will run synchronously with 667MHz RAM. In addition, an advantage that Intel has over AMD is that they design their own chipsets. If they spent the effort, they could easily streamline the CPU-Northbridge-RAM interconnects to reduce latency.
All these are just simple improvements in the buses that will help improve Intel’s performance. Intel’s next-generation architecture isn’t even mentioned, but Conroe, Meron and Woodcrest are certainly something to look forward too. All in all, the delay of an integrated memory controller isn’t a catastrophe to Intel’s roadmaps.
After reading <A HREF="http://theinquirer.net/?article=27317" target="_new">this</A>, I'd like to know if you are still optimistic about Intel's upcoming processors.
Quote :
After all, with its well-know NIH (Not Invented Here) policy, Intel rarely took something from the market that it didn't develop itself, even when it was both technically superior and a good business decision.
This clearly backup what I've said about Intel being an arrogant and foolish company.
Also, you'll have to remember that AMD isn't quiet either.
For the time Intel release their "flagship" processor, AMD will be releasing their much improved quad core processor in 65nm process, extensions to the AMD64 instruction set, all this paired up with Hyper Transport 3.0. and a new multimedia instruction set to boost applications like 3D rendering and audio/video encoding.
My Beloved Rig:
ATHLON 64 FX 55 (will be changed for an X2 3800+)
2X1024 CORSAIR XMX XPERT MODULES
MSI K8N DIAMOND (SLI)
2 MSI 6800 ULTRA (SLI MODE)
OCZ POWERSTREAM 600W PSU<P ID="edit"><FONT SIZE=-1><EM>Edited by Bullshitter on 10/30/05 09:52 PM.</EM></FONT></P>
<A HREF="http://www.theregister.co.uk/2005/10/28/intel_whitefield_india/" target="_new">Here's</A> more info to backup what I've said about a troubled company called Intel...
Quote :
While stunning in its own right, Intel's cancellation this week of the multicore "Whitefield" processor stands as a more significant miscue that simply excising a chip from a roadmap. Whitfield's disappearance is a blow to India's growing IT endeavors.
Originally discovered by The Register, Whitefield stood as a major breakthrough for Intel and its Indian engineers. The much-ballyhooed chip would combine up to four mobile processor cores and arrive in 2007 as the very first chip designed from the ground up in India. In the end, engineering delays and a financial audit scandal killed the processor, leaving Intel to develop the "Tigerton" replacement chip here and in Israel.
El Reg has discovered that Srinivas Raman, former general manager of Intel India's enterprise products group, left the company in early August and joined semiconductor design tools maker Cadence - the home of former Intel global server chip chief Mike Fister. Raman declined to return our phone calls, but insiders confirm that he was the lead of the Whitefield project. The executive became distressed about the project when Intel's audit resulted in close to 50 of his staff being let go from the company, one source said.
Of the 50 staffers, close to 20 of them were sent to India from Portland in 2001 to work on Whitefield. The cancellation of the project has since resulted in much of the work being sent back to Portland.
Whitefield had been meant to serve as Intel's most sophisticated response to the rising multicore and performance per watt movements. The company has fallen well behind rivals IBM and Sun Microsystems on such fronts in the high-end server market and behind AMD in the more mainstream x86 chip market. The Whitefield chip was designed to give these competitors a real run for their money as it made use of Intel's strong mobile chip technology to deliver a high-performing product with relatively low power consumption.
Instead of wowing customers, Intel has disappointed them and created a painful situation for its India staff.
Local paper The Times of India commented this week on the situation.
"India's ambitions of emerging (as) a global chip design and development hub has just suffered a big knock," the paper wrote. "Intel has killed its much-hyped Whitefield chip, a multicrore Xeon processor for servers with four or more processors that drew its name from Bangalore's IT hotspot, Whitefield, and which was being developed almost wholly in this city.
"Intel had invested heavily in the project, both in infrastructure and people, drawing in some of the brightest talents. Some 600 people are said to be employed in the core hardware part of the project."
Chip staffers in India currently fear losing their jobs and morale is very low as a result of the Whitefield cancellation. Many of the staffers had only been told that Whitefield would be delayed by six to nine months. They learned of the project's end in the press.
The difficulties here show how complex global operations can be with sophisticated products. India hoped to take on more and more of Intel's design work, but such plans look iffy now to say the least.
These disruptions hurt Intel during a very difficult period for the company. It had appeared that Intel managed to correct the chip delay issues and strategy mistakes that plagued it during 2004. Instead, the company this week delayed work on both its Itanium and Xeon lines, giving AMD a chance to take even more market share from the giant.
Intel declined to comment for this story
My Beloved Rig:
ATHLON 64 FX 55 (will be changed for an X2 3800+)
2X1024 CORSAIR XMX XPERT MODULES
MSI K8N DIAMOND (SLI)
2 MSI 6800 ULTRA (SLI MODE)
OCZ POWERSTREAM 600W PSU
