Second-class Intel to trail AMD for years

So says The Register.

Read <A HREF="http://www.theregister.co.uk/2005/10/29/intel_xeon_2009/" target="_new">here</A>

I'm really sorry for Intel, but they diserve it for being arrogant and foolish...

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I disagree. There's nothing particularly wrong with most of their processors. It's just that the competition is better for most people.

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XxxxX
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I'm not buying a P4 either. But I'm also not even looking at the P4 articles since their naming scheme makes it very annoying to read.

Eventually the OEM's will figure out what's going on and will start switching over to AMD.

You have to realize though that someone who keeps upgrading within the Intel family of processors is probably happy since to them they are getting an increase in performance. The problem is those that go from Intel to AMD and then try to go back to Intel. That's not fun.

<font color=red><b>Long live Dhanity and the minions scouring the depths of Wingdingium!</b>

XxxxX
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Worse then the Itanium?

Some people are like slinkies....
Not really good for anything but you cant help smile when you see one tumble down the stairs.

It doesn't bother if Intel makes zillion of dollars if they don't know how to use it the right way.

Just look at their roadmap: Delays, cancelled processors and the list keeps growing (don't even mention their actual offerings which are no competition to AMD's processors).

AMD being a smaller company knows how to spend money in a wise way.

What Intel is doing with all that money...
One has to wonder

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Well, Intel can blunder a lot without getting really hurt. They are that rich.
They have monopoly in CPU/Chip-set business globally and they think
they can fuckup in about anything without getting caught.

If in trouble, Intel drops a few GaZillions bucks more to the marketing dep, and pisses on the R&D dep, and orders for more champagne for their owners for making such a brilliant decision.

After reading <A HREF="http://theinquirer.net/?article=27317" target="_new">this</A>, I'd like to know if you are still optimistic about Intel's upcoming processors.

This clearly backup what I've said about Intel being an arrogant and foolish company.

Also, you'll have to remember that AMD isn't quiet either.
For the time Intel release their "flagship" processor, AMD will be releasing their much improved quad core processor in 65nm process, extensions to the AMD64 instruction set, all this paired up with Hyper Transport 3.0. and a new multimedia instruction set to boost applications like 3D rendering and audio/video encoding.

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OCZ POWERSTREAM 600W PSU<P ID="edit"><FONT SIZE=-1><EM>Edited by Bullshitter on 10/30/05 09:52 PM.</EM></FONT></P>

Sadly, that article was posted at 6:53PM so I just missed it by 11 minutes.

I agree that an integrated memory controller is preferable, but Intel can still remain competitive despite the delay. By H2 2006, all Intel's processors will have shared L2 caches in addition to direct L1-L1 interconnects. This will eliminate the need to go through the FSB for cache transfers, freeing up bandwidth for other tasks. The use of shared L2 caches is superior to AMD's current implementation of a Crossbar as no L2-L2 transfer needs to take place therefore eliminating any bandwidth or latency issues that exist despite being within the CPU.

The use of a shared L2 cache also means that data does not need to be repeated. This is one aspect where Intel's architecture is superior to AMD's. While AMD only uses 4-way associativity in their L2 cache, Intel uses 16-way. This means that more of the cache can be accessed at a time. Therefore, information only needs to appear once in a larger L2 cache and can be accessed by both processors instead of being repeated twice in two smaller caches. While this obviously reduces latency as mentioned before, the key thing is it makes a 4MB L2 cache store more information than a 2x2MB cache with Crossbar does by eliminating duplicates. Making L2 cache space go farther in holding data helps Intel reduce constraint of FSB bandwidth as L2 cache hits increase, thereby decreasing the need to access the RAM.

The elimination of the need to use the FSB for cache-to-cache transfers and the higher hit rates in a shared L2 cache means that that the 10.6GB/s bandwidth of each 1333MHz FSB (of which each processor has its own) just may be sufficient. If it isn't, Intel could simply augment a large 16MB shared L2 cache with a 16MB shared L3 cache. The additional cache would further decrease the need to access the RAM and ensure the FSB bandwidth goes further. With a 65nm process, the die size of such a behemoth is probably the same as the current 90nm Xeon MPs that integrate 8MB of L3 cache, so it isn't too unreasonable. In addition, with the pipeline reduction of Intel's next-generation architecture, and the inherent improvements in Intel's 65nm process, adding more transistors for the L3 cache wouldn't jump the power consumption too high. Certainly, it would still be cooler than Intel's current Xeons. The use of sleep transistors in the 65nm process also means the L3 cache could be shut down when not needed further alleviating concerns of crazy heat or power consumption.

In regards to the implementation of HyperTransport in Intel processors, seeing that there is a set time to get a new processor to market, whether Intel decides now to design an entirely new processor to accomodate HT or they stick through their own technology's teething problems, the end result would be a similar time-to-market. It would therefore be best to stick with Intel's own technology, especially if they feel that its potentially superior.

On a side note, I would be interested to see what becomes of Intel's attempt to integrate a northbridge and a voltage regulator into a processor. It is works, this will probably do AMD one better since latency and bandwidth issues would be almost nonexistant. Of course this would add to the price, but it may work for high-end products since they are normally coupled with Intel's best chipset anyways (ie. 955EE Presler and the 975X chipset). I believe Intel was looking for an introduction sometime at the end of the decade. With the use of the 45nm process or something smaller, everything would fit nicely and run cool.

While integrated memory controllers are good for high-end computers, I'm curious as to their effects on low-end systems. Since the RAM needs to be accessed through the processor, I wonder what the effects are to integrated, TurboCache, and Hypermemory graphics cards? The latency will obviously be higher. The problem would now have switched from the processor fighting the addons for memory bandwidth to the addons fighting the processor. I'm sure this will also have an effect on sound cards especially with multichannel and digital sound becoming popular as these requirement quite a bit of memory. This is probably why Creative has taken it upon themselves to alleviate the problem by integrating large amounts of RAM into their high-end sound cards. RAM-graphics card latency issues associated with integrated memory controllers will probably be more pronounced once Windows Vista is released. Since Microsoft recommends at least 512MB of video cache to run with all the visual effects activated, even the most high-end graphics cards today are lacking. Even a 256MB 7800GTX may need to access the RAM through the PCIe bus, through the chipset, through HT, through the processor, through the memory controller, then through the memory bus then to the RAM. How much effect this has compared to going directly through a northbridge based memory controller remains to be seen. Most likely the latency issue is small, but this is the core OS. Even small latencies in the OS will filter through and magnify as applications are run.

Ohh, please...
I've read many articles that can prove you're wrong on this. In deed, a shared L2 cache is not so efficient as many thought to be (it all depends on the architechture). That's the reason why AMD doesn't needs a shared L2 cache thanks to the MOESI implementation.

So, do you believe that large caches are a feature in a processor???

Opteron/Athlon 64 doesn't needs large amounts of L2 or L3 caches because it doesn't suffer from badwidth limitations as Intel does. When I see Intel's roadmap, all I can see is processors with 8MB and 16MB of cache. This is a sign that the processor is starving for data. In conclusion, large caches are a sign of a flawed architecture.

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Agreed. The old way was much easier. Now ah forget it.

Most of us here know that Intel will be back. I, and many others look forward to it. After all, the consumer is better served when there is competition.
Being a part of the market, and not a shareholder, I dont care much who is top dog. I do find it "interesting" though, that people would sacrifice their needs, to maintain a loyalty to a company. This is especially true, when that company is as large, and selfserving as Intel. Amd may not be as large, but a blind loyalty there, would be just as misguided.
Personnally, I would love to see Intel use their FD SOI technology. Performance has been advancing a little slow for my liking.

You are right, it depends on the architecture as everything always does. In this case, Intel is designing the architecture around a shared L2 cache. The concept is being introduced in Yonah, which in itself while building on the Pentium M architecture is quite different from Dothan. Conroe, Meron, and Woodcrest are almost a completely new architecture as is combines Netburst with Pentium M. The use of the shared L2 cache will be ingrained in this architecture by adding new algorithms for L1-L1 and L1-L2 transfers. As well, prefetch logic which is already advanced in the Pentium M and Prescott (one of the few things Prescott is good at), will be further improved. In the end, these features will benefit the processor and reduce FSB bandwidth demands.

In terms of Intel's need for L2 cache, the reason is due to its inclusive architecture. AMD has long used exclusive cache. As such, AMD processors due not benefit much from have large cache sizes. More specifically, will increases in L1 cache size may show larger performance gains in an exclusive architecture, increases in L2 cache does does not. Conversely due to its inclusive nature, Intel processors can show larger performance increases from increasing the amount of cache. Specifically, increases in L2 cache size show larger increases in performance. This nature is why AMD's L1 caches have often been larger than Intel's since that is what they require. AMD's L2 caches are small simply because they are of little benefit even if they were to increase. Intel on the other hand, uses large L2 caches because it allows them to greatly increase performance. The transition from the Prescott 500 series to the 600 series is a bad example since in this case Intel was to lazy to update the caching algorithms to reduce latency and fully take advantage of the additional cache. However, a great example is the transition from Banias to Dothan.

The larger caches in Intel processors are directly due to the architecture's ability to use it to increase performance. This isn't even taking into account the benefit in the reduction to FSB bandwidth. That is just another benefit to Intel's inclusive architecture. Looking deeper, Intel's architecture isn't as flawed as it may appear.

Proved what he links a register link that fortell's doom as it always does. The the thread turns into copy paste opinion and babble.

The fact of the matter is Intel is in no fiscal trouble so the doom can not be soo. Perhaps they will trail for many years its tough to say, really doesnt bother me either way since nothing new interests me.

But hey the registers and mr. bull have forseen the future and know the next 4-7 years of operation for Intel. Lets see if the fortune tellers are correct.

-Jeremy Dach

Yes they'll be. Intel will still have the bandwidth problem no matter how much they increase their FSB (don't even mention 4 and more processor in a multiprocessor system).

Just to burst your bubbles, AMD will include more memory controllers for each core with socket 1207. Pci-e will be embedded on the processor also (this means that graphic cards will no longer be bottlenecked from the processor).

For the time Intel releases their flagship processor (2007-2008), sadly (for Intel), they'll be competing with K10 which will be a different beast than current dual core Opteron processors.

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...And talking about coprocessors (if you've read the article from Anand), <A HREF="http://www.sci-tech-today.com/story.xhtml?story_id=003000002GY3" target="_new">this</A> might be AMD's new approach for their upcoming processors.

I'll be really sorry for itanium if this ever gets to happen in a not so distant future. This will finish put the nail on Intel's coffin (just my personal thoughts).

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OCZ POWERSTREAM 600W PSU<P ID="edit"><FONT SIZE=-1><EM>Edited by Bullshitter on 10/31/05 11:01 PM.</EM></FONT></P>

I think you don't get it dude:

The FSB is out dated!!!

I believe it has about 20+ years.

Intel knows it and they are working really hard to come up with something new.

The easiest way for them is to adopt HTT and include memory controllers on the processors. Anyhow, thay're too stubborn since they don't like the idea of using technology from others. That's why they're suffering now the consequences.

Even Dell is suffering from Intel's problem (we all know that Dell is intel's whore). Read <A HREF="http://www.theinquirer.net/?article=27348" target="_new">here</A>

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Yes well that is thier way of dealing with opteron's chip to chip HTT link. Sad isn't it?
You are aware that the present xeon latency is double what the opteron's is?
You do know that opteron has lower latency to ram, than the xeons have to L3 cache right?
Before you go spewing Intel PR crap around here, or make up imaginary flaws in Amd chips, take the time to understand what you are talking about.

In regards to the L3 cache latencies, I haven't heard that before. Although in truth I'm not that surprised. Intel has a tendency of slapping cache on processors without tweaking their caching algorithms to take full advantage of it. Blunt addition of cache would also result in increased latency. I'd be interested in seeing those benchmarks.

In the case of understanding what I'm talking about, what are you referring too? It is my analysis of the benefits of a shared L2 cache?

http://yara.ecn.purdue.edu/~pplinux/ppsmp.html

This might be a bit dated and based on Linux, but the process of how shared cache works is still the same. The benefits are clear even back then:

"The good news is that many parallel programs might actually benefit from the shared cache because if both processors will want to access the same line from shared memory, only one had to fetch it into cache and contention for the bus is averted. The lack of processor affinity also causes less damage with a shared L2 cache. Thus, for parallel programs, it isn't really clear that sharing L2 cache is as harmful as one might expect.
Preliminary experience with our dual Pentium shared 256K cache system shows quite a wide range of performance depending on the level of kernel activity required. At worst, we see only about 1.2x speedup. However, we also have seen up to 2.1x speedup, which suggests that compute-intensive SPMD-style code really does profit from the "shared fetch" effect."

The concept behind the benefits of shared L2 cache is also explained by X-Bit Labs.

http://www.xbitlabs.com/articles/e [...] 005-2.html

"Mobile dual-core processor manufactured with 65nm technology aka Yonah, which I have already talked about during the Napa platform discussion, will feature Intel Smart cache. Smart cache means shared cache between the two cores. Since we have two cores and we have a single bus, there will also be shared single bus interface. This way both cores can share the same copy of data from the L2 cache. Besides that, the L2 and data cache unit feature improved pre-fetches, i.e. we can do pre-fetches on the per-thread basis, thus ensuring better bus utilization. It also has bandwidth adaptation buffer, i.e. each core takes 4 cycles to adapt.

The difference between independent and shared caches is the following. In case of independent caches the data is transferred from one core to another via the FSB. In case of shared caches the data is transferred directly between the caches, you avoid the bus traffic and synchronization time to get on the bus. This is important for multi-processing systems, because this way you reduce the number of bus cycles involved."

While the article is on the Intel IDF, the blurb above is not Intel marketing, it is the opinion of the X-Bit Labs author of this editorial piece. As well, the improved data-fetching techniques I mentioned which would reduce FSB bandwidth requirements are also mentioned by X-bit Labs. Clearly as I mentioned before, shared L2 caches can greatly benefit multicore processors which is why Intel is implementing it.

The stuff I mentioned about inclusive and exclusive caching and their differences is just very basic background information.

http://www.cpuid.org/reviews/K8/index.php

"The exclusive relationship is the most flexible, as it allows lot of different configurations in keeping a good performance index. The drawback is that the performance does not increase very much with the L2 size. The inclusive relationship can only be chosen for performance purpose, knowing for example that increasing the L2 will create a performance boost."

That is why I said AMD doesn't have large L2 caches, because it wouldn't benefit them much anyways. On the other hand, Intel processors can have large performance gains from more L2 cache.

I hope these external sources satisfy you that there is basis to what I am saying.

Algorithms cant change natural law. The cache can not have a new charge applied before the earlier charge is gone. That would be a short cct.

What analysis? Analysis requires understanding, which you just lack.
Example. The shared cache requires larger cache, which increases latencies. The shared cash requires additional "optimization" to control cache access. While the shared cache has advantages when bothe cores require the same info on cache, this is seldom the case, in real life. The shared cache will need core time, and interconnect time to function. Duh, that's going to require more prefetch, to work, and eat more bandwidth.
Look, if you dont understand what you are reading, ask, someone will be happy to explain. Dont come around spewing Intel disinformation, and expect people to buy it.