the P4 bus is still 100 MHz, and its DUAL channel, that means you must have two RIMMS, one for each channel to be able to allow independent simultaneous access to different blocks of ram. then each channel is dual pumped that makes the *effective* frequency of 400 MHz. Using a 133 MHz real FSB will give 533 MHz of *effective* FSB.
BTW that doesnt mean 4 instructions per clock, it means its able to access memory at these speeds. talking of instructions per cycle, P4 can handle upto 20 instructions at a given time in its 20 stage hyperpipeline and execute 4 instruction per cycle *provided they are all integer and independent of each other*
the question is, with all these heavy memory bandwidth, does the P4 live upto this speed? in early times, cpu needed higer mem bandwidth, and now with bandwidths of the order of 3.2GBps, is the CPU really ready for such speed?
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