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RAM Bandwidth

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  • Bandwidth
  • SDRAM
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Anonymous
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December 12, 2000 9:01:13 PM

I belive the only lesson AMD have to learn from PIV is related to memory bandwidth. For the first time RDRAM showed what Rambus and Intel was claiming for years: RDRAM can offer high bandwidth.
Actually 3.2 GB against 2.1 GB from the latest DDR SDRAM.
If AMD want to fill the gap, I think there are 2 ways:
1. increase SDRAM speed.
2. increase SDRAM bus size.

Increasing SDRAM speed could be a difficult road. 200x2 Mhz DDR SDRAM already exists, which could pair the PIV memory bus speed, but they are expensive, and, because of it, produced in small quantities. So a chipset maker developing a 200x2 chipset could face too small sales.

A 128 bit 133x2 DDR SDRAM would have a 4.2 GB bandwidth.
Enough to smoke even the PIV. A thing like this could be obtained using 2 conventional 64 bit DIMM, and I belive it could cost even less then a PIV + RDRAM. The technology is nothing new because many high end graphic cards use it today. And I've read on Tom's site someone (I don't remember who, maybe Nvidia??) are already planning something like this.

Of course all the above make little sense until a 133x4 FSB Athlon.

What do you think about?

Regards,
Corrado

More about : ram bandwidth

December 12, 2000 9:29:17 PM

What I want to know is what is the bus width between the Northbridge and the PIII or Athlon processor? Is that set by the processor or the chipset?

I mean you could make a 128 bit wide path between RAM and the chipset but it wouldn't do any good if the path between the processor and the chipset was only 64bit. I am asking this question because I am curious as well and I honestly don't know the answer. Could somebody answer this question?

I think the main limiting factor with a 128 bit wide memory interface was the fact that it would greatly increase the number of traces (and pins on the chipset) required on the motherboard, increasing complexity and cost. However, that would be a cost I would be willing to pay for.

Say if it were possible to have a 128 bit wide interface between the processor and chipset, could you imagine an Athlon with 128 bit 166 DDR (333 MHz), with a 333 Mhz FSB double-pumped (667 to CPU)? 128 bit 166DDR SDRAM (333 effective) would be 5.2 Gigs of bandwidth! All you'd have to do is populate 2 DIMMs at a time. Add that to the 667 Mhz path between processor and chipset that leaves a dedicated 5.2 gigs between processor and RAM and the other 5.2 gigs of bandwidth could be divided up between any other peripherals. While your at it, why don't you just double the width of the AGP port to 64 bits? Maybe I don't have a single clue as what I am talking about and I'm sure a lot of people will tell me so, but I think that sounds cool at least!
Anonymous
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December 12, 2000 11:12:37 PM

AFAIK, PIII, PIV and Athlon have a 64 bit FSB (Front Side Bus, the one between CPU and northbridge).

It's not the bit size which should match between RAM and CPU, but the bandwidth.

Take PIV in example:
CPU: 8 byte (64 bit) x 400 MHz (quad pumped 100 MHz) = 3,2 GB/sec
RAM: 2 x 2 byte (2 x 16 bit RIMM) x 800 MHz = 3,2 GB/sec
That's 3,2 GB for both, doesn't matter if RIMMs put it out in 16 bit chuncks while CPU read 64 bit in a whole.

A 128 DDR SDRAM could be:
RAM 16 byte (128 bit) x 266 MHz (DDR 133MHz) = 4,2 GB/sec
This could fit perfectly with a quad pumped Athlon:
CPU 8 byte (64 bit) x 532 Mhz (quad pumped 133 MHz) = 4,2 GB/sec

A 333 MHz FSB seems too difficult to me: it's 2.5 times the actual frequency!
Instead a quad pumped bus seems more feasable: at least someone (Intel) alrady did it.

Regards,
Corrado
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Anonymous
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December 13, 2000 1:21:15 AM

Well, while reading this thread, I find a few problems.

THe EV6 bus that the athlon/duron uses is double pumped, and making it quad pumped would be rather difficult to do. It was designed to be scalable to 200x2Mhz, resulting in an equal bandwidth to the P4, which would be ideal.

Another is some people dreaming about a 128-bit memory interface with DDR RAM. Well, I have good news: nVidia is making a chipset that supports this.
Anonymous
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December 13, 2000 4:11:38 AM

<i>"If AMD want to fill the gap, I think there are 2 ways:
1. increase SDRAM speed.
2. increase SDRAM bus size."</i>

actually, they can simply double the current single channel into dual channel.

dual channel PC1600 DDR RAM will have a bandwidth of 1.6x2=3.2Gbytes/s; dual channel PC2100 DDR RAM, 2.1x2=4.2Gbytes/s.

if you have read tom's recent review of Elsa Gladiac GeForce2 Ultra, you see the real potential of DDR RAM. the Gladiac Ultra features 128bit memoty bus @ 250MHz DDR. this config's bandwidth is: <b>8Gbytes/s</b>!!!

then what is the potential of RDRAM? the highest spec of RDRAM we've ever heard of up until now is still PC800 (800MHz internal clock frequency), with a ultimate bandwidth of only 1.6Gbytes/s. a dual channel of PC800 RDRAM can only reach 3.2Gbytes/s. that is all about (and the end of) the Rambus crap.

plus RDRAM's meager 16bit interface (32bit if dual channel) and (in)famous latency issue, i really can't see Rambus is the way to go. this is also why Rambus Inc. wants to be the royalty collector for DDR technology so desperately.

wait and see. Intel will also take the DDR route in near future.


-----------------------------
Some are ignorantly happy,
While some, happily ignorant.
December 13, 2000 3:34:47 PM

Is that Nvidia chipset only going to be for the PIII or will they have a version for the Athlon as well?

Plus I don't know how they are planning on getting that bandwidth to the PIII CPU. It was designed for an SDR interface. How are they going to increase that? Can they force the fsb to go double or quad pumped? How does the CPU recognize that?
December 13, 2000 4:06:17 PM

Yeah, but what happens if Rambus develops specs for RDRAM with a 64bit or 128 bit interface like SDRAM has? Then we're talking about 6.4 GB/s or even 12.8 GB/s bandwidth. It'd be hotter than Hades, but it would smoke too.

And what if RDRAM got switched to a .13 micron process and then upped their clock frequency to even 1GHz?

You have to admit that at the moment SDRAM sounds much better. But, in the future RDRAM might be more advanceable and not reach the same bandwidth walls that SDRAM will hit.

But then, we also have to see if anyone can develop quad-pumped SDRAM. Wouldn't that be the truely ideal memory for a P4? (And for whatever chip AMD creates in the future that is quad-pumped?)

- Sanity is purely based on point-of-view.
Anonymous
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December 14, 2000 12:10:44 AM

don't worry, d00d...:) 

new wider interface will just be way much more difficult to implement. we haven't heard of 32bit, 64bit or any higher spec RDRAM yet, but we do have 64bit, 128bit and even 256bit interface SDRAM, which can be easily made into DDR versions. actually, Tom's new review of Diamond Fire GL2 has already featured a 256bit memory bus interface @ 120MHz DDR.

but a wider bus interface is just way too much more expensive. RDRAM with a meager 16bit interface has already been infamous for its rediculously low yields and high cost, any wider interface version will simply be less worthy of mass-production.

.13 process will be great. it will also benefit SDRAM and DDR RAM, maybe even more than it will do RDRAM.

last but not least, Rambus Inc. squanders way more of its time, money and other resources on ligitation than on R&D. do you think a 32bit-interface or .13 RDRAM will come any time soon?


-----------------------------
Some are ignorantly happy,
While some, happily ignorant.
Anonymous
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December 15, 2000 7:54:19 PM

AFAIK it will support Athlon only.
Anonymous
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December 15, 2000 9:05:32 PM

One small note, RDRAM doesn't have 800MHz internal clock. The 800 is referring in part to the overall bandwidth, hence the reason why DDR memory doesn't refer to its clock for speed but bandwidth as well.

<A HREF="http://www6.tomshardware.com/mainboard/00q4/001030/athl..." target="_new">http://www6.tomshardware.com/mainboard/00q4/001030/athl...;/A>

There's a link to page that briefly refers to it. Sorry, can't find the definitive one I remember. It's at the very bottom of the page.

"The answer is not in your hair."
"I'd rather jump in the lava than be fragged by you."
December 16, 2000 1:04:02 AM

DDR-RAM's PC spec does refer to it's bandwidth (ie. PC2100 = 2.1 GB/s), but RDRAM's PC spec is the actual <b>clock frequency</b> (ie. PC800 = 800Mhz). The reason it's bandwidth isn't like 800Mhz SDRAM would be is because its data bus is only 16-bits wide (SDRAM has a 64-bit data bus). PC800 RDRAM has a bandwidth of 1.6GB/s which is equivelent to PC1600 DDR-RAM. RDRAM gets 3.2GB/s by using two RIMMs in dual channel configuration.

Here is Tom's RDRAM review: <A HREF="http://www6.tomshardware.com/mainboard/00q2/000529/inde..." target="_new">http://www6.tomshardware.com/mainboard/00q2/000529/inde...;/A>
Anonymous
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December 16, 2000 6:26:44 AM

thank you, yoda, for explaining this for me. however, i have one point to add.

my saying PC800 RDRAM has an internal clock frequency at 800MHz is a bit misleading. it's just like saying Pentium 4's got a 400MHz FSB (now we know it is only a "quad-pumped" 100MHz FSB). the PC800 RDRAM's 800MHz actually comes from a "double-pumped" 400MHz clock frequency. this means that RDRAM uses DDR technology internally. this is also why, i guess, Rambus Inc. so strongly pushes that they are the owner of the DDR technology.

-----------------------------
Some are ignorantly happy,
While some, happily ignorant.
December 17, 2000 7:35:58 AM

DDR2 is 3.2 G/s per module...
But its in development...


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-<font color=red><b>R.K.</b></font color=red>
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