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A few questions

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January 19, 2001 4:55:39 PM

Okay, I've got a few questions relating to the CPU.
I've worked on computers all my life. (Ever since I had a C=64 at age 7.) I can build a PC from scratch with one hand tied behind my back. I can overclock with the best of them. And I've been a C/C++/MFC coder for five years. So I KNOW computers.

But I realised the other day that one thing still baffles me.

What in the world are a FSB and multiplier in terms of physics? I know how they work to calculate a computer's speed. But what I don't know is what the physics relationship is between them. HOW do they make the computer faster?

And another completely unrelated but still on topic question:
Everyone knows that the new Celerons are just P3s with half of the cache disabled. I don't have a problem with Intel doing this because they're a business and out to make money. So I can even respect them for doing it instead of just lowering the prices of P3s to that of the Celerons.

But does anyone know how to re-enable that half of the cache so that you can buy a P3 at a Celeron price? Now THAT would be useful information.

- Sanity is purely based on point-of-view.

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January 19, 2001 5:50:16 PM

Did you also program in assembler? Only THEN you know computers!

It may very well be that half of the cache is disabled because of a defect on the chip. This way the chip can still be sold at a lower price instead of trashing it.
Of course I'm just guessing on this, but I know some manufacturers of memory chips (did) use this practice.
January 19, 2001 6:51:57 PM

I had the joy of upgrading 16-bit x86 assembler code to 32 bit x86 assembler code. Even though I only worked in it for six months, I did have the joy(?) of working in it.

Actually, it wasn't all that bad if you don't mind constantly looking up what interupt you need in a book and don't mind writing twenty lines of code just to perform a task that could have been done with one line of C++ code. I didn't mind then. It was my job. :) 

I did mind though that I had to replace a lot of the code with calls to other routines because Microsoft was no longer supporting all of the DOS interupts in their DOS emulation built into Windows95. That sucked.

And if Intel is selling damaged P3 chips as fully working Celeron chips, I have even more respect for them then to make a good product that people want out of something that might otherwise have been thrown away. I always enjoy seeing creative ways of making a profit.

Unfortunately, if that is true, it'd mean that people can't just connect the dots with a pencil and get the other half of their cache back. That's bad. So I hope that isn't the case. Not that I need a new chip myself. I just always enjoy seeing ways to bend rules.

So I guess either way I'd get joy out of it. But I'd prefer the latter as other people would get joy out of that as well.

- Sanity is purely based on point-of-view.
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January 19, 2001 9:06:14 PM

The Celeron is castrated at the Eratta level. once a P3 is confirmed not up to spec its cache gets clipped and retested @ new celeron safe levels.

Lets look at the 800Mhz P3, the E and EB state the FSB and type of core. E is for CuMine and B is for FSB or BUS speed.

800EB is 6multiplier x 133Mhz FSB
800E is 8multiplier x 100Mhz FSB

As FSB speeds gotten faster over the passed few years, reduction in multiplier was needed to compensate for increased speed on the bus without pushing the CPU beyond its capabilities.

You cannot change the multiplier unless you have a "engineering sample" or a "Intel Confidential" that is "unlocked". there were a few early celerons (266, 300) that had unlocked FSB.

The 133Mhz FSB CPU will beat the 100Mhz FSB counterpart in most tests.

Now that we know that current production CPU's can achieve 133 FSB easy. we buy the 100Mhz version and overclock them increasing FSB to 133Mhz + producing a 1Ghz CPU.

If we used a 800EB that has a 133FSB by default, overclocking gets harder as memory requirements go up to unsafe levels. You might be able to hit 150Mhz FSB producing a 900Mhz CPU.

If you dont plan on overclocking go with the 133FSB CPU
January 19, 2001 10:29:25 PM

Actually what fugger says is correct, however, all celerons are not defective p3's some are simply perfectly good p3's with half the second level cache disabled. As Intels yields increased they had less bad p3's to use for celerons, which, in order to keep up with demand for the celerons causes them to use good p3's. And to this date no one has come across away to re-enable the celeron's cache.

A little bit of knowledge is a dangerous thing!
January 22, 2001 11:44:54 AM

Well, I guess it makes me feel better that so far no one can actually answer any of my questions. That means at least I don't know anything less than everyone else. :) 

- Sanity is purely based on point-of-view.
Anonymous
a b à CPUs
January 22, 2001 12:57:59 PM

you sound like you know your stuff anyway so this you may already know but the FSB is just the frequency of the sine wave that is taking data to and from the cpu how they multiply this I have no idea. If I have got this completly wrong give me a break as it is my missus that is the scientist not me.......

M

one of the first UK T-Bird users....
January 22, 2001 1:26:27 PM

Actually, that does sort of make sense. I figured it was something along those lines, but was hoping for a confirmation.

The multiplier itself confuses me greatly though.

I mean normally I would think that the multiplier would be how many cycles the CPU could perform between the FSB data transmissions. But then I get confused on how adjusting it really high would help any, because you would think that the CPU would end up just constantly looping and wasting cycles as it waited for new data to come in over the FSB.

So I figure I must either still be missing some key element to the way computers work, or else no one really needs a computer with a high multiplier because the CPU is hardly ever going to be able to effectively use it anyway, as it will always be waiting for data transmissions.

But then, maybe that is right which is what the quad pumping that the P4 could solve and would make AMD's double-pumped chips obsolete soon because no matter how high their GHz ratings would get, they wouldn't be able to communicate with the rest of the computer fast enough to actually do anything better than a 1.2 GHz chip could do. (Or something like that. I'm not sure where the actual barrier of pointlessness would be, but you've gotta think that if this theorizing is right than a multiplier of 12 is already really pushing the limits of having any value.)

But if that were right, then you would think DDR SDRAM would have a lot more impact than it is having and it would be the vertiable savior of AMD chips. And that it would work amazingly well in a P4 system as well. (Though not as amazing as QDR SDRAM would.)

So it all gets me confused because it seems like no matter how I look at it, I can't fit all of the pieces of the puzzle together.

Either my assumptions and educated guesses are wrong and PC chips can improve a lot still, or I'm right and soon CPUs are going to be limited by a FSB that just isn't fast enough and they'll get to the point where increasing the speed becomes pointless if it's done only by increasing the multiplier.

- Sanity is purely based on point-of-view.
Anonymous
a b à CPUs
January 22, 2001 1:41:01 PM

"But then, maybe that is right which is what the quad pumping that the P4 could solve and would make AMD's double-pumped chips obsolete soon because no matter how high their GHz ratings would get, they wouldn't be able to communicate with the rest of the computer fast enough to actually do anything better than a 1.2 GHz chip could do. (Or something like that. I'm not sure where the actual barrier of pointlessness would be, but you've gotta think that if this theorizing is right than a multiplier of 12 is already really pushing the limits of having any value.)"

I think you are pushing the limits of your knowledge or lack there of.(no offense) Predictions are made with little/nothing to go on(in your case), theories are based on relevent well researched information. You are basing your prediction on a limited understanding of bus frequency technology. Research it some more before you start 'theorizing'. As for predictions those are free.

Keep posting any new info cause I have a good idea of how it works and would like to know more.
January 22, 2001 2:18:39 PM

Get off your high horse.

I explicitly said that I WASN'T sure such is the case. And that they were only theories, assumptions, and so forth.

And you have the definitions of theory and prediction very mixed up. Theories are educated guesses of a prediction or law of nature based on partial data awaiting future proof. Predictions are educated guesses based on facts.

In both cases, neither a theory nor a prediction is ever said to be true. They are just educated guesses. And fact obtained in time will tell if they are right or not.

But until that time that they are proven right or wrong, they can be discussed and fine-tuned into a better accuracy and more plausability and can acquire circumstancial evidence that supports their case without actually proving it.

And I'd really like to know what other people think about what I've been talking about to refine the theories and maybe even acquire proof (or at least circumstancial evidence).

I would also love to hear anyone give us some facts that either support or disprove any or all of it.

And if you have a problem with it then just ignore it. No one is forcing you to participate. So go bugger off unless you can actually contribute something useful instead of your negativity.

- Sanity is purely based on point-of-view.
Anonymous
a b à CPUs
January 22, 2001 2:23:45 PM

I understand that they are working on several different advances in the CPU/ Data transmission world, one of which is Photon based CPU's this allows the internal bus to blow anything we have now to tiny bits, and the other is Quantum CPU's they have the made a data but arrive before they sent it but the problem is how do you use it?? the out come would be defined before your input...Spooky
The Photon based units are much more likely to be seen in a few years I will make sure the wife keeps me informed of anything she hears of so I can let everyone know..

As for the CPU's with a high multipier being use less as far as I am aware that is where the internal cache comes into play, it basically buffers the instructions(ie why the duron tops out on speed lower than the T'Bird) so as the multiplier goes up the effective gain per multiplication comes down....
but again most of this is made up from bits of knowladge I have picked up from all over the place so I can't give a complete picture...

M


one of the first UK T-Bird users....
Anonymous
a b à CPUs
January 22, 2001 2:54:56 PM

I thought I might try to help a little.

The FSB controls inter-communication of the individual components on the board, north/south bridges, pci/agp busses, memory bus etc. it's just the way of syncronising the data between points. The data on the lines is read on the edge of each clock pulse, this allows the data enough time to stablise after it is asserted on each line. This is one reason behind the limitations of overclocking; there comes a point where the clock rate is such that data within computer is not getting read correctly on each clock pulse as it is coming along too soon after it is asserted to have stablised properly. (I can go into more detail on this subject along with other reasons if you want).

The clock multiplier is there for a very good reason, it has been possible since the old intel 486 (DX2/66 and the like) to clock the processor faster than the external bus. Because the internal lines, connections, and transistors on a chip are so small the clock rate can be pumped up substantially without making the processor unstable. Why you would want to do this is deceptively obvious; you don't have to access the memory for every calculation. While you are still accessing the memory every intruction, this is usually well cached. The main thing about programs is that they tend to spend a lot of time in loops doing fairly banal calculations on data held in the registers. If you clock up the processor you can make these bits finish faster, thus allowing the computer to complete the bits between the memory accesses in a shorter time. This is a really over-simplified picture but it is accurate enough without having to fill a book!

You are right, though, there does come a point of diminishing returns, that's why AMD and Intel are trying to boost the FSB.

Here's an interesting fact, the Motorola 7400 processor running at 500MHz usually outperforms both AMD and Intel's x86 processors running at 800MHz or more. It's down to a substantially better architecture. Basicly, x86 sucks!!! Doesn't stop us all (including me - Duron 700) using them though does it!

I can elaborate on all of this if you want, but if you are really interested then find a book on digital electronics, and, probably more use, a good book on computer architecture. I would definitly recommend Hennessy and Patterson's book "Computer Architecture: a Quantitative Approach" (ISBN:1558603727). It's pretty much the computer architecture bible.

Also if you go to <A HREF="http://arstechnica.com/cpu/index.html" target="_new">http://arstechnica.com/cpu/index.html&lt;/A> they have lots of info on various parts of computer architecture.

Hope that helps,

Fat Chucky
January 22, 2001 7:09:21 PM

That actually does help. I mean a lot of it I had sort of gathered, but never put together in the whole picture quite as clearly.

So a clock cycle occurs every so often. The faster the FSB, the more often. All of the components of the computer communicate to each other every clock cycle.

The CPU runs faster than the clock cycle so that it can process more information before needing to communicate with everything else again.

So say a CPU has a multiplier of 8, that means that it could (approximately) do 8 times as much work in the time that standard memory could process 1 command.

Or something close to that anyway.

And a dual-pumped CPU can send and recieve data twice during a clock cycle instead of once like standard components, so that it would pick up on new information being present faster and would assure it's commands are picked up right at the beginning of the next clock cycle.

And DDR SDRAM does the same. So (in theory) an Athlon system with DDR SDRAM both with the same FSB could send and recieve data between each other about twice as fast as they could communicate with any other component in the system... IF they only talked to each other. But if they are dependant on recieving data from a slower component than themself, then they have no choice but to wait for it to catch up with them. (Such as the PCI bus.)

Is this sounding right?


- Sanity is purely based on point-of-view.
Anonymous
a b à CPUs
January 23, 2001 12:35:42 AM

Sorry for stating your erata for the rest of the forum to see and that it obviouly pissed you off.
Your definitions are wrong. If you bend rules they can be used in that manner, but it is still wrong.

Your information on how FSB works is obviouly flawed cause you are assuming that what the fellow said about sine waves is absolutly true(partly true by the way- its a little more complicated than sine waves). You take this ity bity piece of information and start 'theorizing' on the performance penalties in processors. For example, I could 'theorize' that due to a 33 mhz increase in FSB, the real world performance of the memory sub sytem etc. would increase by 33% over 100mhz bus. That would obviously be wrong. Should I have theorized, No. Is it a theory no. Is it a prediction yes.

You obviouly have never done any meaningful research(i.e. university labs). So I suggest you sit down, shut up and wait for someone to answer your question adequatly before you start 'theorizing'.

As for the question you asked, it is a good one. I don't have a full understanding of how it works. I am waiting for someone who does to post. So that I can then make inferences on the performance penatlies/bonuses designated to each processor type(if I feel like it).

The high horse I am on is to keep myself from sinking in the knee high [-peep-] some of you guys keep shoveling out your mouths and through your keyboards.


Have a nice day.
Anonymous
a b à CPUs
January 24, 2001 9:25:31 AM

Glad to be of service...

I was a little frazzled when I replied to your posting as I had just finished an exam, so I think I'll make things a little clearer. I've a bad habit of switching between terms that mean the same but sound different!!!

<So a clock cycle occurs every so often. The faster the FSB, the more often. All of the components of the computer communicate to each other every clock cycle.>
Yup, the FSB isn't so much faster or slower as clocked at higher or lower rate, it's a subtle difference, but an important one. Effectively, the data transfers always happen at the same speed, just more frequently with a higher clock rate.

<The CPU runs faster than the clock cycle so that it can process more information before needing to communicate with everything else again. >
The CPU still operates on the clock cycle it's just that the clock rate is multiplied up from the FSB clock before being applied to the inner workings of the chip. The CPU is clocked at a higher rate so it can do extra stuff while waiting for memory transfers etc. to be carried out (in theory!). The trick is to request for data, say from memory, do some stuff while you are waiting, and be ready to play with that data when it arrives.

<So say a CPU has a multiplier of 8, that means that it could (approximately) do 8 times as much work in the time that standard memory could process 1 command.>
Sort of! Memory doesn't so much process commands as reply to requests. You've heard of CAS and RAS ratings? They dictate how long it takes for data to appear on the data bus after a request (latency). CAS 2 rated memory takes 2 FSB clock cycles to assert the data for the processor CAS 3 takes 3. That's why getting CAS 2 memory is always good plan.

<And a dual-pumped CPU can send and recieve data twice during a clock cycle instead of once like standard components, so that it would pick up on new information being present faster and would assure it's commands are picked up right at the beginning of the next clock cycle.>
Pretty much, though, as you say, it's only the stuff close to the processor (memory etc.) that this is effected by this, the PCI and AGP busses work at a lower rate. The funny thing about DDR RAM is the CAS latency hasn't changed (it has effectively got worse in some ways). This means that when the processor requests data from RAM the CAS 2 DDR RAM still takes 2 clock pulses before asserting the data. That's the equivilent of four data transfers though! Most books make memory technology a nightmare to read about, but <A HREF="http://www.arstechnica.com" target="_new">http://www.arstechnica.com&lt;/A> has a very good series of tutorials explaning memory technology in great detail (including how static, EDO, SDR SDRAM, DDR SDRAM, and Rambus RAM work), it's well worth a read.

<And DDR SDRAM does the same. So (in theory) an Athlon system with DDR SDRAM both with the same FSB could send and recieve data between each other about twice as fast as they could communicate with any other component in the system... IF they only talked to each other. But if they are dependant on recieving data from a slower component than themself, then they have no choice but to wait for it to catch up with them. (Such as the PCI bus.)>
Spot on, but remember about the latancy problems so it's a wee wait as the memory searches out the page in memory and then it thumps out a burst of data at the high rate (a burst).

Just as a matter of interest, it's memory latency that dictated some of the design choices for the P4. You probably know that the P4 has what's considered a cripplingly small level one cache? Well this is because the intel engineers wanted to keep the latency on the cache as low as possible. Most level one caches (like on the PIII and Athlons) run with a latency of 3 (three processor clock cycles before the data is ready, a bit like CAS 3 but at the rate of the processor's clock), but because there is less silicon to search with the smaller cache on the P4, its L1 cache has a latency of 2. So the P4 should be able (with a good cache algorithm, which does have) to get the data in the cache to the processor faster with little difference in hit rate.

Woah, that's a lot, I hope I haven't rambled too much - a bad habit ;-).

Regards,

Fat Chucky
Anonymous
a b à CPUs
January 24, 2001 9:50:25 AM

In regards to whether or not a celeron can be turned into a p3, true, some of the celerons are perfectly functioning p3s that have been converted into celerons, but what they do to the p3 involves fusing certain parts of it with a laser, so I'd figure the process is irreversible. :( 

<P ID="edit"><FONT SIZE=-1><EM>Edited by redgoat3 on 01/24/01 06:52 AM.</EM></FONT></P>
Anonymous
a b à CPUs
January 24, 2001 9:56:44 AM

Give the guy a break, he made guesses, so what? It's important to communicate your level of understanding to get a meaningful answer that covers what you need. I do suspect that it was the manner of your posting that caused offence, not the actual points made (it offended me, and it wasn't even directed at me!).

<For example, I could 'theorize' that due to a 33 mhz increase in FSB, the real world performance of the memory sub sytem etc. would increase by 33% over 100mhz bus. That would obviously be wrong. Should I have theorized, No. Is it a theory no. Is it a prediction yes.>
If you want to be totally accurate, theories are a form of prediction (look up any good dictionary/thesaurus). Theoretically you could get this kind of performance increase, we know this is wrong (the theory has no real basis in fact, but intuitively it makes sense), it doesn't stop it being a theory.

<You obviouly have never done any meaningful research(i.e. university labs). So I suggest you sit down, shut up and wait for someone to answer your question adequatly before you start 'theorizing'.>
Ouch, this is really rude. I have answered his questions, and his "theorising" was very useful to my formulation of my answer.

Oh dear, I think I've got a bit stroppy. No offence taken, I hope.

Fat Chucky
!