P4 with 4.266 GB/s bandwidth?

Raystonn

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From http://www.rambus.com/general/press_releases/pr_010508.html

"Samsung Electronics has been at the forefront of RDRAM memory production and is committed to delivering the highest performance memory products to our leading-edge customers, such as Vitesse," said John Kang, Senior Vice President at Samsung Electronics. "We are confident and ready to support the 1066MHz RDRAM speed bin and expect that with our expertise in RDRAM production, yields will be very reasonable. Already, Samsung has components available in sample quantities."

As the next step in the evolutionary roadmap, the 1066MHz RDRAM is a simple bin split of the industry standard 800MHz RDRAM currently available from leading RDRAM manufacturers. The 1066MHz RDRAM delivers 2.1 GB/s of bandwidth from a single device, and is initially targeted for consumer, graphics and communications applications that will benefit from the increased performance, bandwidth and scalability using one to four devices mounted directly on the motherboard.

Samsung plans to support customer demand for 1066MHz RDRAMs in the third quarter of 2001. Yields of 1066MHz RDRAMs will continuously increase as Samsung moves to finer design rules for third generation RDRAMs. Two other RDRAM manufacturers, Elpida Memory Inc and Toshiba Semiconductor, have also announced plans to support 1066MHz RDRAM. All three manufacturers will support both the 800MHz and 1066MHz speed bins in 2001.

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Memory bandwidth just keeps getting better. :) All the Pentium 4 will need to take advantage of this faster memory is to up the 100MHz frontside bus clock from 100MHz to 133MHz. This will give us a quad pumped 533MHz frontside bus with 4.266 GB/s of total memory bandwidth. I believe there may be a DDR solution that will provide around 4.2GB/s bandwidth as well some time in the future. Let's just keep it all coming!

-Raystonn

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Raystonn

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Can you show me a URL to this? I'd like to take a look at the details. Thanks.

-Raystonn

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Pettytheft

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Good I hope there is competition between DDR and RDRAM now. We will all benefit from people pushing the envelope of technology.

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<A HREF="http://www.google.com/search?q=pc2700" target="_new">http://www.google.com/search?q=pc2700</A>

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Raystonn

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Ok, I checked out some details. Looks like PC2700 DDR is running at 333MHz instead of PC2100's 266MHz, for a bandwidth of about 2.7GB/s. That's not a very large improvement. It doesn't come close to PC800 RDRAM's 3.2GB/s or this new 4.266GB/s.

I have heard of QDR ram though, but I haven't yet seen any details. I look forward to massive bandwidth increases across the board, for all technologies.

-Raystonn

= The views stated herein are my personal views, and not necessarily the views of my employer. =
 

ksoth

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You've gotta remember though, 4.266 GB/s RDRAM is dual channel. Sure 2.7 GB/s DDR SDRAM isn't close, but it is possible that dual-channel DDR SDRAM chipsets will appear with dual-channel configurations. Doesn't the way nVidia's GeForce 3 handle memory increase bandwith by like double? I forget what it's called, I think "cross-bar memory architecture" or something, I'll try and look some more. Maybe nVidia's "crush" chipset handle memory the same way as the GeForce 3, possible allowing PC2700 have 5.4 GB/s total available bandwith, although the Athlon maxes out at 2.7 GB/sec at 333 mHz, but I'm sure more won't hurt, considering the i840's performance is better than i820's performance, even though Pentium IIIs bandwith is less than (I believe) what PC800 RDRAM can deliver. 1033 mHz RDRAM is just weird. Why 1033 mHz over 1000 mHz? Oh well, doesn't matter. It's not like faster isn't better :).

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ksoth

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I read about nVidias memory handling system, the "crossbar memory architecture," a little bit more here: <A HREF="http://www.anandtech.com/showdoc.html?i=1426&p=6" target="_new">http://www.anandtech.com/showdoc.html?i=1426&p=6</A>. Basically what it does is makes memory system much more efficient, so instead of wasting 256-bits for a 64-bit memory call, it fetches it using only 64-bits of bandwith instead of using the full memory path. Now, the way it does this is by using 4 32-bit memory controllers instead of 1 128-bit controller. Now, is this in effect a quad-channel memory controller, twice as efficient as the dual-channel RDRAM configuration? Or is the way RDRAM is controlled in dual-channel configurations a completely different type of architecture? Now, what I remember about a dual-channel RDRAM config is that each stick of memory has it's own pathway to the CPU. Is that correct? If so, then nVidias Crossbar Memory Controller is different, and just makes memory calls more efficient instead of increasing bandwith, but I guess it would have a much similar effect. Any input would be appreciated. Thanks.

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Raystonn

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"1033 mHz over 1000 mHz?"

1066 (not 1033) is what you get when you move the P4 from a 100MHz fsb clock to a 133MHz fsb clock. It's the next logical step. I'm just happy we're seeing increases so soon. :)

-Raystonn

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<P ID="edit"><FONT SIZE=-1><EM>Edited by Raystonn on 05/08/01 11:07 PM.</EM></FONT></P>
 
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"1033 is what you get when you move the P4 from a 100MHz fsb clock to a 133MHz fsb clock."

Ummm, I thought the P4 had a 400 Mhz frontside bus. Or was that all a bunch of advertising hubba bubba? Like that kick ass "Net-Burst"
 

Raystonn

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"I thought the P4 had a 400 Mhz frontside bus"

The clock signal is 100MHz. The system bus is quad-pumped off the clock signal, making it 400MHz.

"a bunch of advertising hubba bubba... Like that kick ass 'Net-Burst'"

Intel's NetBurst micro-architecture is actually full of great technology. It features a 400 MHz system bus, Hyper-pipelined technology, rapid execution engine, execution trace cache, advanced transfer cache, advanced dynamic execution, and enhanced floating point/multimedia Streaming SIMD Extensions 2. If you have a question about any of these things, feel free to ask. There are too many go and explain them all here in a single post.

-Raystonn

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Ncogneto

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But you still lose the bandwith war with dual channel DDR vs dual channel Rambus. More bandwith less latency. Why did you not address that point of Ksoth's Thread?

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Ncogneto

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Here is a very good article on the p4 and some definate very interesting explanations on its specperf results.

<A HREF="http://www.aceshardware.com/Spades/read.php?article_id=25000195&keyword_highlight=p4" target="_new">http://www.aceshardware.com/Spades/read.php?article_id=25000195&keyword_highlight=p4</A>

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ksoth

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8x133 = 1066, not 1033. 1033/133 = 7.7669172... Weird multiplier. Are you sure RDRAM clock is a multiplier of the FSB clock? Because if so, what is the multiplier number, and where does PC600 and PC700 RDRAM come in? I don't think RDRAM clock is in sync with the system clock...

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Raystonn

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It's PC1066, not 1033. The 1033 was introduced, probably as a typo, by Ksoth. The FSB of the Pentium 4 runs at quadruple the clock. The clock is 100MHz, the FSB operates at 400MHz. RDRAM is a form of DDR memory, running at twice the speed of the FSB. This gives it an effective 800MHz speed. (Hence the name PC800.) The data bus of RDRAM is 16-bits (2 bytes), thus giving us a 1.6GB/s sustained data transfer rate per channel.

When PC600 RDRAM is used (ew), the clock is probably run at 75MHz instead of 100MHz, quadrupling to a 300MHz FSB, and thus doubled to an effective 600MHz by the RDRAM. PC700 RDRAM would require an 87.5MHz clock.

PC1066 will require a 133MHz clock.

-Raystonn


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Raystonn

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"But you still lose the bandwith war with dual channel DDR vs dual channel Rambus. More bandwith less latency."

If they are able to create dual channel DDR and surpass the bandwidth available by RDRAM at the time it's introduced, then we'll get some really kick 'donkey' benchmark scores for our processors. :) RDRAM would still give you less latency during normal and high memory usage, but I would probably still go with whoever provided the best bandwidth for the system; even if it is DDR SDRAM.

I will never lose the bandwidth war because I'm not attached to any specific type of memory. I don't wear a fanatic cap. ;) If a new technology comes along with better bandwidth, I'll be all over it.

I am a bit concerned regarding dual channel DDR. Due to its parallel nature there will be a great deal many more pathways to etch on the motherboard. This could well make motherboard manufacturing quite a bit more diffficult, possibly raising prices on the motherboards. We'll have to see where the prices go.

Another interesting scenario is that with the low pathway count of RDRAM (because it is serial), it's not too unreasonable to suggest a quad channel RDRAM motherboard. The downside of this would of course be the requirement that every channel must have at least one memory module installed. We would be required to fill 4 slots at once. I suppose we could have 8 open memory slots on a motherboard to allow for upgrades without discarding any modules.

All of this brings me to another observation. A dual channel DDR implementation will require 2 memory modules be installed, just the same as a dual channel RDRAM implementation. So far DDR has continued to allow only 1 memory module to be installed, because there is only one channel. No longer will this be a benefit of using DDR over RDRAM.

-Raystonn

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Ncogneto

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RDRAM would still give you less latency during normal and high memory usage,
This is not entirely correct. It all depends on the type of access made to memory, just as much as the amount of memory usage. Also, with a dual channel DDR interface, even this issue will be addressed as well.

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leonov

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"RDRAM would still give you less latency during normal and high memory usage"

This is not actually true in normal operation. The performance depends entirely on HOW the memory is accessed. Random memory access is by far the most prevalent way that memory access occurs and the poor performance of the P4 across many benchmarks shows just how bad RDRAM is in this area. This is precisely due to its high latency. Incidentally this is why Intel are trying all sorts of methods to decrease latency in the Northwood chip by using on-die memory controller, larger L2 cache, potential use of L3 cache and use of SDRAM (and DDR SDRAM). By "normal and high memory usage" ("medium" has become "normal" now I see) you may be referring to sequential access of memory whereby the hardware prefetcher has a very significant impact in reducing the average latency. Such memory accesses occur in programs which use large regular blocks of data such as video and graphics processing.

I will see if I can dig up the link to an article I read recently. It clearly shows that bandwidth is not the most important factor in good application performance, low latency is FAR more important in the majority of apps.

As far as motherboards being more difficult to make for dual DDR SDRAM chipsets this is true but the problems come from trying to make the propagation delay equal across all the traces. The number of traces is not really a problem as such.

BTW As I cannot be bothered to dig up the other thread I will just say that I agree with you that a P4 upgrade for existing systems is possible in future. However changing both the processor AND the motherboard is hardly what people normally mean by upgrading the processor. You might just as well upgrade to an AMD chip!

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Sojourn

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I would imagine the latency penalties would get very very high for an 8 slot configuration, as with RDRAM the latency has to be synced with all loaded DIMMs, which means they all run as though they were the farthest DIMM.

It will also be interesting to see if RamBus has any cards left to play as their legal battles play out over the next few months. The complete win by Infineon certainly doesn't bode well for RamBus' other litigations. If Infineon wins its $100M suit for damages, pending this week, RamBus may not have a whole lot of money to invest in any kind of R&D as the rest of the industry lines up to take their bite out of the tech-nazis.

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ksoth

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But what about the Pentium III??? You had PC600, PC700, and PC800 all running off a 133 mHz FSB? No quadruple-pumping of the FSB clock. I did some reading and the RIMM clock is seperate from the system clock, and it is up to a memory interface on the chipset's memory controller and the RIMMs themselves to determine the speed. PC800 is fed off a 400 mHz clock, PC700 is fed off a 356 mHz clock (effectively 712 mHz DDR, not 700), and PC600 is fed off a 266 mHz clock (effectively 532 mHz DDR, not 600). So, basically the FSB of the Pentium 4 and PC800's 400 mHz clock is just coincidence, as I'm sure Pentium 4's will also work with PC600 and PC700, and it is also probably only coincidence that he next RDRAM speed grade is PC1066, off a 533 mHz clock, and I'm sure PC1066 will also work with today's Pentium III and Pentium 4 systems. Here are some sources I used:

<A HREF="http://www.anandtech.com/showdoc.html?i=1239&p=3" target="_new">http://www.anandtech.com/showdoc.html?i=1239&p=3</A>
<A HREF="http://www.tomshardware.com/mainboard/00q1/000315/rambus-01.html" target="_new">http://www.tomshardware.com/mainboard/00q1/000315/rambus-01.html</A>

That's weird I typoed 1066 to 1033. Oh well. Pretty good reading. :p

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ksoth

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You're right. Looking at Rambus' financial portfolio, they only have $138 million cash on hand. But, they are one of the most profitable companies out there, on a percentage basis. While Intel and AMD are working off about 25% and 20% profit margins respectively, Rambus has an amazing 71.7% profit margin!!! That's insane to me. Not to mention they have huge asset and equity returns of 42% and 57% respectively. But, given they only had $110 million in sales this past year, they don't make too much money. The thing is though, Rambus sells licenses, that's all. They do no manufacturing or selling of actual products.

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Raystonn

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"I would imagine the latency penalties would get very very high for an 8 slot configuration, as with RDRAM the latency has to be synced with all loaded DIMMs, which means they all run as though they were the farthest DIMM."

The 8 slot example about which I was theorizing had 4 channels. Latency only increases when you add more chips on the same channel. The latency would be equivolent to what we have in today's systems.

-Raystonn

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Raystonn

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They frontside-bus speeds aren't necessarily synchronized by necessity, but as a matter of optimization. Balanced bandwidth is important in eliminating bottlenecks.

-Raystonn

= The views stated herein are my personal views, and not necessarily the views of my employer. =