faster bus speeds than today's
Why is it that bus speeds now days 100( or 200 DDR) and 133( or 266 DDR) are found common? Cpu speeds have been increasing but why cant the bus speed be also increased. I'm not talking about overclocking.
The problem is that everything on the board changes when you increase it. That's why the P4 is a quad-pumped 100 bus, not a true 400 bus. I guess they just haven't figured out how to get everything going independant of each other. Or maybe they don't want to, for some reason.
Apple? Macintosh? What are these strange words you speak?
As you increase the frequency of the bus, propergation delays through the printed circuit board tracks start becoming significant not to mention problems with parasitic capacitance and inductance.
If you were to have a real 400 mhz bus the electical signals would behave more like radio signals and leak through to adjacent tracks?
Maybe we are reaching the frequency limits for the bus until someone develops a real light based puter then our P4 systems will be real stone age relics!
can't board makers put some kinda frequency limiter between the chipset and a (say) hard drive or PCI slot, so that the frequency of those components remains the same, but that of rest of the system increases.
And if we need to increase the frequency (speed at which hard drive will talk) of hard drive we can adjust that by the component between the chipset and the hard drive (if for example umda 166 comes out).
thats what they already do... pcis are supposed to run at 33mhz... compared to a cpus 66 100 or 133... when you overclock with the fsb the pci clock also goes up... making some cards die temporarily... the fsb on processors is going up alongside the actual clock speed... the celerons staryed at 66mhz fsb until the 733... i think the 800 was the first 100mhz fsb celeron... amd are doing the right thing... allowing for faster bus speeds and the chipsets support it... when a faster bus comes out on a processor there will be a motherboard to support it... motherboard manufacturers wont want to make independently adjustable clocks for everything as it will increase the price of the chipsets a bit too much and synchronisation will become more of a problem causing more instabilities...
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The reason for increasing FSB speeds? From what I understand, it's a matter of attempting to remove the CPU-RAM bottleneck. Now that the CPU-RAM bottleneck is beginning to become less of a problem (right now, there little <i> real-world </i> difference in the double-pumped 133MHz link of AMD or the quad-pumped 100MHz link of Intel), the FSB speeds will level out at 100-133MHz, and the slot speeds will begin to rise, so that, in the case of the PCI slot, there isn't a 300% difference in MHz (PCI @ 33MHz).
Beyond the technical problems of increasing the bus speed, there is also the practical problems. While it would be great if you could get a comp. to have a true 400MHz FSB, as long as you still have the PCI, AGP, ISA, and other such slots, you're going to have to have a divider in there to pare down the speeds so that you don't kill your cards. Right now, 133MHz will probably be the most for around a year, but I wouldn't be surprised if a 166 or 200MHz came round in 18-24 months (it looks good, and it helps out marketing). But, until those slots are upped to new standards (a PCI-like slot @ 66, or 100MHz even, AGP-like slot @ 133, etc.), those FSB speeds will only affect the data link between the CPU and RAM. Now, that's good for office tasks, and other CPU and RAM intensive programs, but for programs that require the unified systems (i.e. gaming, CAD, servers, anything that uses a periphial card extensivly, etc.) this is only a small piece of the pie (quite important though).
Now, I might be wrong in saying that (good chance actually), but I still think, that since there was a time when the PCI and AGP slots were at, or half of the FSB speed, there will again be a time when that happens. Memory link is important, but I think that for a truly monumental overall system performance increase, a complete redesign of the card slots is needed, so that they can operate on par with the CPU-RAM link.
lets face it, we are reaching the limits of FSB.
basically, FSB is the frequency that the processor is supposed to communicate with the outside world, not just memory. so all the other parts on the motherboard work at a fraction of his FSB, and any increase in it will increase their speed. some older pci cards might not work at even slight overclocking, even at 40 MHz. although the PCI2.1 specs say that the PCI bus can run at 66 MHz, very few card run at that speed and still fewer chipsets support it.
you can select the divisor for the pci/isa bus for the system bus, so that it could run at its rated speed although the system might run at higher speeds.
but then, speed on a board has its limits. the capacitance on the epoxy and inductance of the tracks already limit the frequency by imposing some latency and distortion that increases with increasingly higher frequencies.
besides, consider a 100 MHz bus. its cycle time is 10 nS. thats 10E-8 seconds, and light travels a tiny distance of less than 3 meters. the elecrtical signal can travel still lesser, and still lesser given the latency. besides, it has to arrive some time before its actually read in, thats the setup-time by definition. all the signals on the bus have to reach their destination at the same time. so you can see chipsets mounted at 45 degree orientation, so that the track lengths are not too different on the same bus.
with increasing frequencies the situation becomes too difficult. the only solution to this problem is to integrate as much circuitry as possible on the silicon into the chipsets, and make the motherboard as small as possible. since there are no such limitations as yet on the silicon where the signals have to travel microscopic distances.
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did you ever heard off long lines (propably wrong translated) but at an higher frequentie the max lenght of a wire where you still can see the output (the signal) is being decreased as the frequentie creased so in other words if they increase the bus the signals that the processors sends to its outer regions (pci) will not get there. did you guys never wonder why the agp bus is close to the processor and the motherboard chip? otherwilse
option 1 is to include more onto the chip itelf - integrate in silicon, but what about increasing bandwidth between memory and cpu. Kind of the plan for RDRAM and QDR I think, multiplex or increase the bus bandwidth to more and more channels. Rather than increase the individual frequency of the path, increase the capacity of it for multiplexing.
Regarding 100Mhz FSB - I cannot think it is that great a challenge to break by an order of magnitude since we have network links 10x faster over both copper and fiber. I realise there is more to it than just that due to timing and syncronisation but...
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yes, the AGP is kinda super-advanced PCI bus running at 66 MHz and it being closer is just a matter of design. 66 MHz is not a frequency you need to watch out too much. I have seen boards the CPU placed on the other edge of the board whereas the AGP being at its usual place, the third bracket from the top.
one more problem with faster bus speeds is that 100+ MHz running all over the board tends to radiate radio signals or RFI that have to be minimised (high quality chassis are rated for RFI suppression), that can cause problems with different hardware as well as other communications.
what you really need is to increase the bus width, to say 128. that will double the bandwidth at the same freqency. and whats there, double pumped buses are nothing but aggregated bandwidth busses, two banks work in parallel to provide double speed of data transfer.
and the last thing, these speeds are no way near to the minimum, theorotically, you can make a bus with speed as high as 1 GHz, which will allow the signals to travel less than 30cm, which easily is just the lenght of an average motherboard.
but now consider this: the pcb material, glass epoxy, for that matter any material - is a dielectric. just any conductor is not a perfect conductor, any insulator is not a perfect insulator. this dielectric creates capacitive impedences all over the board, across its two sides, between adjacent tracks, adjacent connectors. the long lenghts (of the order of 25~50cm) tracks pose inductive impedences. the result? distortion in the signal at its receiving end, which could be reduced by incresing the voltage. but incresing in voltage? we all think those guys are after reducing the voltage requirements to reduce heat and thus reduce the chip sizes. then those who know digital electronics know there has to be some time called setup-time that the signal has to reach before its actually asserted. and this time is not in any proportion to teh bus speed, but depends upon the material, the fabrication process and the kind of device.
the problem with the board emitting radio waves will be even more prominent at 1 GHz.
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Buissness reason, RAM makers had no reason to push the envelop when prices were high. People needed more RAM as software requirments increased even if it wasn't faster RAM. CPU, GFX, and software makers on the other hand are in a do or die situation. If they don't make faster, better products people have no reason to buy more and the company's die.
Now look what's happened now that prices are low and RAM makers are in a do or die situation. We have attempts to raise prices by introducing new RAM types like DDR, and within a year we will see PGA DDR modules running @400MHz, with DDR-II close behind.
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