L1 Cache - The P4 's True Weakness?

I've been reading some of the tech info on the Pentium 4, and the design doesn't seem to be as weak as people say it is. The number of pipelines isn't a bad thing as long as mispredictions are minimized. The only true weakness I could find is the L1 Cache design. It's both ingenious and stupid. The Pentium 4's L1 cache virtually eliminates latency! The disadvantage is that it's too small. Today's applications are not designed to work well with small caches. What Intel needs to do is at least double the size of the cache to make the Pentium 4 perform well. Well, anyway, that's just my speculation. Anybody have any other thoughts about this matter?

AMD technology + Intel technology = Intel/AMD Pentathlon IV; the <b>ULTIMATE</b> PC processor
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  1. I had played with that idea, problem with it is the P4 integer does well. I'm not sure, I think more L1 would probably help tho...

    ----------------------
    Independant thought is good.
    It won't hurt for long.


    edited twice, I can't spell for crap tonight...<P ID="edit"><FONT SIZE=-1><EM>Edited by 74merc on 08/14/01 11:03 PM.</EM></FONT></P>
  2. is maybe true that 8 KB of L1 cache is not very good.For overall that the best cpu avaible for pure performance.P4 come from 35 point behind in sysmark with P4 1.4 now with 1.8 he in advance of 20 point.
    That 55 point of gain with 400 mghz and a new stepping new nvisia driver.All driver bios are still young.Like R200.
  3. what do video drivers have to do with sysmark?

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  4. it needs at least 32k or more of L1 and 512k of L2, especially if it is to work with DDR and SDR.

    its ALU is too fast that it is at times starved of instruction bytes even with 3.2GB/sec RDRAM!

    girish

    <font color=blue>die-hard fans don't have heat-sinks!</font color=blue>
  5. 20 bit pipeline... hello anyone? a bit too long... there was an article about the g4 architecture compared to the p4 architecture somewhere and they put the blame on the extremely long pipeline which wastes clock cycles... oh well... shorten the pipeline, add a few dozen kb of l1 cache... a meg and a bit of l2 and should be fine... and the price tripled or so... do you know how much cache costs to implement?

    if in doubt blame microsoft...
  6. The 20 stage pipeline is necessary to ramp up clock speeds on the chip. It may make the P4 suffer in the short run due to branch mispredictions, but in the long run it will be able to scale much higher than the previous 17 stage pipeline of the P3. Sooner or later AMD will also have to implement a longer pipeline in order to raise the clock on their chips, I am sure AMD will also take a performance hit due to this, it is only a matter of time.
  7. oh you mean ludicrously high clock speeds which dont mean a thing because of the lengthened pipeline which is NOT needed to pump up clockspeeds but makes it easier...

    if in doubt blame microsoft...
  8. ou mean this artical right
    <A HREF="http://arstechnica.com/cpu/01q2/p4andg4e/p4andg4e-1.html" target="_new">http://arstechnica.com/cpu/01q2/p4andg4e/p4andg4e-1.html</A>

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  9. thats one which mention the problem but thats not the one i was talking about no...

    if in doubt blame microsoft...
  10. Quote:
    it needs at least 32k or more of L1 and 512k of L2


    And P4s aren't expensive enough already? Well, I suppose since OEM computers are around 1/3 of what they were 5 years ago (for 10x the CPU clock speed), it's still not very expensive. But anyway, that would add a lot of cost to the processor. I wouldn't mind paying out the nose for something that really kicked butt, but I don't think it'll happen, with AMD breathing down their neck.


    <font color=blue>Quarter pounder inside</font color=blue>
    <font color=red>Change the Sig of the Week!!!</font color=red>
  11. nothing i just write the change all that have change the score of P4 remeber specwief (something like that)once lose new driver now equal now he faster.
  12. boy oh better thats.

    <font color=blue>THG needs 2 change the sig' of the week errrr century!</font color=blue>
  13. I think AMD will eventually have to raise the number of pipelines as well to achieve higher clock speeds.

    AMD technology + Intel technology = Intel/AMD Pentathlon IV; the <b>ULTIMATE</b> PC processor
  14. longer pipe? they should learn from the P4, 20 storey pipelines dont perform well except allow you to raise the raw clock. and that is evident from the result of Tbird 1.2 vs. P4 1.7 match!

    staying low will help them counter the scraper and better. and I think they know that.

    girish

    <font color=blue>die-hard fans don't have heat-sinks!</font color=blue>
  15. they currently have <A HREF="http://www.cs.nmsu.edu/~myu/pipeline.htm" target="_new">10</A> (15 for FP/MMX). 20 is too much, i guess they'd settle for 16.

    <font color=blue>die-hard fans don't have heat-sinks!</font color=blue>
  16. Remember Intel is all about marketing though. If they can easily get 1.8 instead of 1.4, they'll do it. Even if performance suffers.


    <font color=blue>Quarter pounder inside</font color=blue>
    <font color=red>Change the Sig of the Week!!!</font color=red>
  17. Yeah, probably in that range. They also have to be clock competitive with Intel, you know. Not everybody out there understands IPC (instructions per cycle).

    AMD technology + Intel technology = Intel/AMD Pentathlon IV; the <b>ULTIMATE</b> PC processor
  18. but somebody out there has to get the awareness among the commons. perhaps AMD could do a stunt like those infamous PR ratings. then the Athlon 1.4 will be labelled as Athlon P4R 1.9!!!

    <font color=blue>die-hard fans don't have heat-sinks!</font color=blue>
  19. more cache means bigger die size, means less quality yields, means higher price, and the P4 is already 2 damn expensive.
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