AMD 200 FSB Argument... Prove im right

G

Guest

Guest
OK

I have a AMD Duron 800
Gigabyte 7ZM KT133 Chipset
128 pc-133

Supdmuffin says i need DDR MEM to run my bus at 200MHz bus
i say i dont.. All durons, Athlons run at 200MHz bus BASE.

right? even with pc-133 mem?


I have a 200 MHz bus and its running at 200 MHz with pc-133 mem and a KT133 Chipset right?

Explain this so people know


--call it what you wish, with this machine I can make mercury flow in 3 directions at once--
 

AmdMELTDOWN

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man, I always thought you had a tbird, I think spud is right but maybe I'm wrong:), I've heard of the incapabilaty's of the kt133 chipzat or is that the kt133a? LOL!

"<b>AMD/VIA!</b>...you are <i>still</i> the weakest link, good bye!"
 

madmike

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That depends on which bus you're talking about. This might help settle the argument: <A HREF="http://www.webopedia.com/TERM/b/backside_bus.html" target="_new">http://www.webopedia.com/TERM/b/backside_bus.html</A> I take it what you mean by BASE is backside bus. In that case, you're right - your backside bus (L2 cache) is at 200MHz and the frontside bus (memory) is at 133MHz.
 
G

Guest

Guest
hmm
more info needed pls

--call it what you wish, with this machine I can make mercury flow in 3 directions at once--
 

mpjesse

Splendid
Yes and no t-bird. The bus between the northbridge and processor is actually 100mhz (200mhz DDR). Now, with PC133 the bus between the northbridge and memory is actually 133mhz. With DDR, it would be 266mhz.

So, while the FSB is 100mhz (200mhz DDR), the ENTIRE bus is limited to the speed of the memory- which is 133mhz.

-MP Jesse

"Signatures Still Suck"
 

74merc

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read a new book.
that is an arguement for older PC's, where the L2 cache resides on the motherboard, but the L2 cache of nearly ALL current processors L2 cache runs at full processor speed.
his FSB is running 100Mhz DDR, it has roughly the bandwidth of a high latency 200Mhz FSB. His memory is only running 133Mhz, low latency. His FSB is capable of moving 1.6gigs per second, his memory is capable of 800megs per second.
Neither will ever hit that theoretical number unless they somehow manage to magically remove all latency from the system.

----------------------
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It won't hurt for long.
 

Schmide

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Well yes and no. The bus between the Northbridge and the Processor is a clock for clock 200mhz x 72bits (64bits data 8bit ECC) = 1600MBs transfer rate. There is no rising or falling edge for the transfer and should be considered SDR. Because of the point-to-point nature of the EV6, multiple transfers may be active at the same time, up to 24 simultaneous transfers per processor to be exact. Although the memory speed of the system is clocked at 133x64=1024MB sec, the processor is not resigned to just communicating with main memory. Thus transfers between devices may often run in parallel and thus utilize close to the full FSB.

Schmide