I've been told by my sources at Intel that the Celeron has SMP disabled. But he didn't say how.
The Celeron starts it's life as a PIII and then, if it fails the cache test on one side, the connections are blown on that side. So it wouldn't surprize me if the did a similar thing with a communications link that lets two processors communincate.
I'm so tired of cookies I'd settle for spam!