It looks like we're finally going to be squeezing more than a single bit at a time from each wire. It's about time!
<A HREF="http://www.hardwarecentral.com/hardwarecentral/reports/1973/" target="_new">http://www.hardwarecentral.com/hardwarecentral/reports/1973/</A>
Almost all component interconnect technology today transfers data using 0's and 1's represented by voltage levels. Traditionally a "1" was presented by 5 Volts and a "0" by 0 Volts. RSL used a reference voltage of 1.4 Volts, wherein a "1" was presented by 1.0 Volts and "0" by 1.8 Volts. QRSL uses four voltage levels to represent two bits of information: Logic 10, 11, 01 and 00.
This multi-level signaling technology allows higher bandwidth, double that of RSL, without increasing clockspeed. In this case, a single memory device is capable of providing up to 3.2 GB/s of memory bandwidth, using only a 16-bit databus. If scaled upwards to a 64 or even a 128-bit databus as often used in today’s videocards, this comes to:
64-bit / 16-bit = 4 : 4 x 3.2 = 12.8 GB/s for a 64-bit databus
128-bit / 16-bit = 8 : 8 x 3.2 = 25.6 GB/s for a 128-bit databus
--------
I can imagine we will end up with at least 8 distinct voltage levels representing a full byte per wire in the not-so-distant future. That will be an 8-fold increase over today's bandwidth without taking into account adding more pins (wires) or increasing clockspeeds. In my opinion what we need is more of these new algorithms and technologies. They are much more effective than simply pushing the old stuff with higher clockspeeds and increased pins.
-Raystonn
= The views stated herein are my personal views, and not necessarily the views of my employer. =
<A HREF="http://www.hardwarecentral.com/hardwarecentral/reports/1973/" target="_new">http://www.hardwarecentral.com/hardwarecentral/reports/1973/</A>
Almost all component interconnect technology today transfers data using 0's and 1's represented by voltage levels. Traditionally a "1" was presented by 5 Volts and a "0" by 0 Volts. RSL used a reference voltage of 1.4 Volts, wherein a "1" was presented by 1.0 Volts and "0" by 1.8 Volts. QRSL uses four voltage levels to represent two bits of information: Logic 10, 11, 01 and 00.
This multi-level signaling technology allows higher bandwidth, double that of RSL, without increasing clockspeed. In this case, a single memory device is capable of providing up to 3.2 GB/s of memory bandwidth, using only a 16-bit databus. If scaled upwards to a 64 or even a 128-bit databus as often used in today’s videocards, this comes to:
64-bit / 16-bit = 4 : 4 x 3.2 = 12.8 GB/s for a 64-bit databus
128-bit / 16-bit = 8 : 8 x 3.2 = 25.6 GB/s for a 128-bit databus
--------
I can imagine we will end up with at least 8 distinct voltage levels representing a full byte per wire in the not-so-distant future. That will be an 8-fold increase over today's bandwidth without taking into account adding more pins (wires) or increasing clockspeeds. In my opinion what we need is more of these new algorithms and technologies. They are much more effective than simply pushing the old stuff with higher clockspeeds and increased pins.
-Raystonn
= The views stated herein are my personal views, and not necessarily the views of my employer. =