Celeron II's ARE PIII's. They take the PIII's with defective cache and disable the defective side by "blowing" connections with high electrical current. Then they apply the multiplier locks and the tag.
All Coppermines do indeed come off the same line. Including PIII's and Celerons. If they won't run within heat tolerance, they are set at a lower clock. The cache is the most defect-prone part of the chip, if one side is bad, it is disabled. Everything that makes the difference between a Celeron 566 and a PIII 1000 happens during the final testing process, where certain circuits are blown to make the bus speed and voltage differences. You can understand that part if you look at the white papers. I don't know how the multiplier is set though. If I did I might be able to change it.