Memory bandwidth and the K63

Ok, a lot of you are here from the 8.4 memory bandwidth thread and this applies to you in particurlar.

DDR SDRAM and RDRAM, no matter how you put it ar DRAM types, Dynamic Ram that is.

A little history on DRAM: Early in the days of personal computing, in the long long ago, when memory was first developed there was SRAM. Static Ram- this later became known as cache and can be found on almost all processors (I am excluding the registers of course, the Cyrix MIII i believe has no onboard cache [not the Via C3 -64kb]). But back then it was the only Ram solution. So back in the day, people got a thinkin: this stuff is good but way too expensive to make. And so they created DRAM, a cheap, low efficiency, high power drain, version of SRAM. From then on computers have used DRAM in various forms.

FYI SDRAM is a combination of DRAM and SRAM, with better performance than DRAM, but lower cost than SRAM.

Now, given the fact that SRAM and all other microcircuitry is becoming dirt cheap, don't you think it would be logical to go back to the old SRAM standard?

Where the K6III comes in:
Remember the K63, that was a while ago- i know. But how do you think that something that was in essence a k62 was able to compete with a P3 at the same clock speed? Simple- the K63 used an L3 SRAM external cache buffer (think pentium 1 ). In fact think all pentiums!!!

Pentium 1 - external cache blocks.
Pentium pro -same deal
Pentium II - Slot chip, the packages had external cache chips on them next to the processor)
Pentium III- same deal.

RDRAM, DDR nothing. If you want performance SRAM is where it's at.

Case in point : TUALATIN PIII!

:eek: <font color=blue>I for one run Quake 3 on a P133(No MMX)</font color=blue>I have no affiliatioin w/ Intel

- Btw, the Slot Athlons also had SRAM external cache.<P ID="edit"><FONT SIZE=-1><EM>Edited by AlphaSan on 09/20/01 09:56 PM.</EM></FONT></P>
9 answers Last reply
More about memory bandwidth
  1. I have a couple thoughts I'm interjecting since I'm a bored loudmouth. Drag me through the mud if you can, I seem to enjoy it. Keep in mind, and am not a really silicon guy (but if the opportunity arose, however...), so you probably can't really sue me, or anything.

    Your question was./?:

    Now, given the fact that SRAM and all other microcircuitry is becoming dirt cheap, don't you think it would be logical to go back to the old SRAM standard?

    My answer is.:

    I think it's a great idea assuming it's feasible/useful and, if it get's us where I believe we are obviously headed i.e. to an ultrawide RAM/Processor FSB bandwith goal, and with the ratio of instruction execution cycle to memory access cycle time equal to one being the ideal limit. It all really depends on who can come up with the best and cost effective processes for attaining the goal. If it's SRAM then so be it. Read on if you care to see me try to explain a what I mean a little.

    You'll find I tend to promote carrying this to the extreme, in other words the magical ratio of one I mentioned. I've heard seemingly believable arguments against what I propose, I just don't believe them. i.e. 94%(ballpark, guess for current Athalon/Pentium instruction executor/main memory interface caching algorithm efficiency) efficiency is good enough. Some may consider me blasphemous. All I can say is give me the resources and I'd give er a good try. The design I'm going to describe is the only way to get 100% "PC" efficiency. I happen to think this would be worthwile for performance reasons, but this is just my gut feel as I obviously can't prove it due to my last name not being IBM or something.

    One nitpick, sorry, but basically this is related to what I'm basing my whole reply on. I have to disagree with when your labelling SRAM's "caches" as many PC's use SRAM as system RAM, but maybe my definition of a PC is a little loose.

    A Question:

    I haven't seen large fast SRAM's have you?

    By fast I mean CPU core speed or so. By big I mean big enough to hold all concurrent applications in RAM. If so we're set, we can get rich. Yeehaw.

    Here's the plan. We'll steal a good processor design and design our own custom circuit.

    I'm thinking we need to be on die asic(sp?) style or similar, SRAM running full clock speed as RAM, registers, buffers, and etc., am I leaving something out? Add hardware for a few instructions to the CPU. Take a few instructions out of hardware since we're saying bye bye L1, and L2 type cache/controlling hardware, hey hey.

    OK, then we make Motherboards. Someone nice optimizes some software for our wicked fast, ultra tiny, shiny new "PC".

    And the crowd goes mad.

    no kidding.
  2. YOu started out OK, got switched in the middle, and then forgot that the Coppermine PIII/Celeron II as well as the Duron and T-Bird use the same type on ON DIE cache as the Tualatin.

    Back to you Tom...
  3. SDRAM is not a combination of SRAM and DRAM. The S in SRAM stands for Static. The S in SDRAM stands for Synchronous. SRAM is Static RAM. DRAM is Dynamic RAM. (Static and dynamic are opposites.) SDRAM is a form of DRAM that is synchronous.

    SRAM is very fast but also continues to be extremely expensively. Sorry, but it is not dirt cheap as you seem to believe. This is why caches are limited in size in processors. As you increase the cache size, you greatly increase the cost of the processor.


    = The views stated herein are my personal views, and not necessarily the views of my employer. =
  4. Sram requires I believe 6 transistors per bit, whereas dram requires 1 transitor per bit.(not counting control circutry) thus to have 256Mbit of sram requires 6 times the transistors of the equvalent dram, not to mention the extra wiring and more chance of failure those extra transistors ad to the equasion.

    Sram is spendy, hence is is only used in certain special applications(like cache etc)

    "The Cash Left In My Pocket,The BEST Benchmark"
  5. In response to all (i think) of the above posts, if i miss anything, tell me:

    I think you missed my point about the Tualatin. I brought it up to show how much cache (SRAM) improves performance. The difference between the coppermine and the Tualatin is quite big, don't you agree? As an example of pure SRAM this does not apply since the cache is internal. That's why i brought up all the Slot CPU's which have cache chips inside the slot package.

    As for SDRAM i believe the initial design called for DRAM with an SRAM buffer. Since then we have begun to see unbuffered versions and the original design has come to be known as Registered SDRAM. Am i right?

    Matisaro- I see what you are saying. But i do believe that DRAM uses 4 transistors per bit. Of course your point is valid: SRAM would be more expensive to make than SDRAM but look at how cheap memory prices are today- would it really be that expensive to produce SRAM?

    As for large SRAM blocks: i know that 2Mb cache modules are available for all Pentium/PPRO/K6X series of processor, and are pretty cheap. The largest cache block i've seen on sale at was 64mb. So....

    i guess that's that...

    :eek: <font color=blue>I for one run Quake 3 on a P133(No MMX)</font color=blue>I have no affiliatioin w/ Intel
  6. Sorry, i didnt get any response from you guys, so i figured it was pushed off the front page.
    Don't kill me for doing this, as i will only do this ONCE. never again -

    :eek: <font color=blue>I for one run Quake 3 on a P133(No MMX)</font color=blue>I have no affiliatioin w/ Intel
  7. No, I am 99% sure dram uses 1 tranistor per bit, it keeps refreshing to maintain the data storage, go to for their dram theory and black paper article to confirm.
    ::too lazy to find link::

    "The Cash Left In My Pocket,The BEST Benchmark"
  8. Speaking of SRAM. The Nintendo GAMECUBE has about 24mb of T1-SRAM in it for system memory. Thats a big load of SRAM.

    Nice Nvidia and ATi users get a Cookie.... :smile: Yummy :smile:
  9. The t1 sram is kind of cool, it has less transistors per bit than regular sram, therefore its cheaper, but it runs at the same speed. Nintendo rocks. (probably switching to ati if radeon 2 pans out, I am an old school nintendo fan and am ashamed that nvidia would pander to m$ for the xcrap.)

    "The Cash Left In My Pocket,The BEST Benchmark"
Ask a new question

Read More

CPUs Bandwidth Memory