A challenge for Intel

Well, we all know why P4 crawls even when it has the luxury of 3.2 GB/sec of memory bandwidth and a double pumped ALU (Rapid Execution Engine).

Its the 20 deep Hyperpipeline that is negating all the memory bandwidth and other architectural advantages it has over others. Even with a superior branch prediction algorithm that hits as much as 98%, every new branch of code has to go through all the 16 stages to actually start executing. Imagine you are in a que for train tickets at a crowded station and the clerk suddenly shuts his window out for lunch when you are at the window, and you have to go back and stand at the end of another que and wait for your turn all over again!

It actually got them to make processors running at higher MHz, but this long instruction tunnel held back the performance somewhat, to such a extent that even a 1 GHz P3 or Athon can beat a 1.5 GHz P4 hands down.

But when you consider that the P4 Netburst architecture is evolving now into its second version - the Northwood which is supposed to perform better than its predecessor Williamette, you see a distinct improvement in design. The design is in process of maturing.

Its the branches that are bothering the P4 performance, I guess there can be a solution to this. Remove the branch prediction unit out right. Put in a third (or even a fourth one for back to back jumps) execution pipe alongwith the existing two and work both code paths, whether the code branches or falls through. It will practically reduce the branching and the penalties incurred due to it to zero!

Its difficult to implement, especially managing three or more execution pipes when they have no mutual priority over each other.

A few more things could be increasing the cache, tweaking up the ALU, prioritising regular instructions and multithreading complex ones. Executing FP, MMX and SSE/SSE2/3DNow class instructions asynchronously with code will also increase performance largely.

Just like a we have a graphics processor these days, it would need a complex hardware operating system within the processor, which is more than regular microcode and nanocode, maybe a picocode!

I guess AMD, Intel have already thought it over.

girish

<font color=red>No system is fool-proof. Fools are Ingenious!</font color=red>

a new core will do, netbust is busted.

the bat is in Athlon's hand right now!

<font color=red>No system is fool-proof. Fools are Ingenious!</font color=red>

I think Jerry would just shrug that one off, since he was left for dead in a trashcan when he was in college. It just doesn’t compare. It was her fat bodyguard anyways.

Schmide

Girish,

Good read.

Obviously you have thought about this one a little. What you said has piqued my interest. I'm not going to pretend like I understood all of that. I'll probably have to sleep on that one. You got any good books or links to share? Call me a nerd, but it sounds interesting to me, and I want to know more. Unfortunately I'm probably going to have to start at the beginning on this one.

Kevin

Weeeeeeeelllll, I thought I should talk about their strategy on silicon!

Anyways, current Intel pricing is competative enough theough it could do away with about still 30%. Besides, Intel has one distince advantage over AMD, its brandname established over more than 30 years. People buy intel because they know intel. They are ready to pay for it. AMD evened by keeping their chip prices low. With that AMD did make a dent in Intel sales. Now they should compete on technology, intel is already on a price cutting mision.

But still, they need to show that a 2000 MHz processor performs as 2000 MHz, and no processor running as much as 600 MHz slower can beat it.

girish


<font color=red>No system is fool-proof. Fools are Ingenious!</font color=red>