Intels BBUL packaging

[mr_gobbledegook]

After reading Anandtech’s article on Intel’s BBUL packaging I would say Intel are making big leaps in processor packaging. I was quite interested where Anandtech started talking about the benefits of BBUL in relation to AMD’s sledgehammer….

Source: <A HREF="http://www.anandtech.com/cpu/showdoc.html?i=1542" target="_new">http://www.anandtech.com/cpu/showdoc.html?i=1542</A>

<font color=blue>”The benefits of this type of packaging can also be extended to multi-core CPUs. One of the major problems with outfitting a CPU with two cores is that the two must be tested together in the final CPU and if just one is bad, the entire CPU must be thrown away (AMD's SledgeHammer will unfortunately face this problem it seems). With BBUL you'll be able to embed two CPU cores using two separate dies and connect them with an internal high-speed bus, giving you the benefits of a multi-core CPU but also allowing you to test the cores individually before packaging them into a single CPU.”</font color=blue>

Since Intel are in direct competition with AMD it seems AMD will not be able to use this technology unless it is licensed out (at a huge fee of course). So what are AMD going to do about it ?

IBM’s Power4 processor apparently has two cores and I was wondering how they got around this problem.

I know AMD will use Silicon on Insulator (SOI) which was developed by IBM for their Hammer processors; will this solve AMD’s multi core manufacturing problems?

Are IBM currently using SOI for their Power4 processors and if so how successful is it ?

P.S Apparently Intel will be releasing a 1.8Ghz Celeron (based on P4) early next year. If this is the case what will the P4 Northwood be running at ??! 2.4-2.6Ghz maybe ??!
Source: <A HREF="http://www.theregister.co.uk/content/3/22144.html" target="_new">http://www.theregister.co.uk/content/3/22144.html</A>

<font color=purple> **Life is too short to be pissed off all the time.**</font color=purple><P ID="edit"><FONT SIZE=-1><EM>Edited by mr_gobbledegook on 10/10/01 08:35 AM.</EM></FONT></P>

 

[AmdMELTDOWN]

pretty cool Intel tech right there, Intel won't be forced anymore to give away lic's to *MD because of the FTC, *MD will have to do it the old fashioned way and design it themselves.

but if *MD wants Intel to fab their cpu, maybe that can be worked out!

IBM's Power4 is an exceptional design, I hold IBM up there with Intel in term of innovations and great products!

IBM Power4 is two 64bit cpu's, has SOI with about 7 layers of cooper at .18micron

IBM's 64bit cpu will be way better than *MD's imho.

Intel's new celeron will be 1800+ williamete core and the Northwood will come out this quarter starting at 2000+ netburst™ speed

"<b>AMD/VIA!</b>...you are <i>still</i> the weakest link, good bye!"

 

[charliec2uk]

Ahh, you saw that article too. Did you see the references to Intel's Prescott core. What I want to know is whether this is another core revision for the P4 or what and if so what will this bring?

Democracy Bernad, it must be stopped!

 

[charliec2uk]

Hmm, AMD have innovated a couple of things. They were obliged to write their own 387 micro-code which seems to have stood them in good stead.

What about Apple. True they have to be *different* but they have made some big contributions to the industry. The GUI to name one.

But that is academic, tell me, have you see or heard any references to the Prescott core. I reckong that this is a another core revision for the P4, have you heard anything about.

P.S. I really reckommed the book "Inside Intel" (Tim Jackson) to you, not least because it tells a good story of teh rivalries between the two companies.

Democracy Bernad, it must be stopped!

 

[Matisaro]

Chips are tested before they are packaged for functionality, hammer will be 2 cores on a single chip, as far as the outside world is concerend it will behave as a single chip, therefore this issue is a non issue, if one of the cores in the hammer is a failed die, then the whole thing is scrapped ANYWAYS, and this is determined before packaging.

~Matisaro~
"The Cash Left In My Pocket,The BEST Benchmark"
~Tbird1.3@1.5~

 

[FatBurger]

but they have made some big contributions to the industry. The GUI to name one.

Xerox made the first GUI interface and the first mouse. Microsoft and Apple were both there (Bill Gates and Steve Jobs, perhaps), and saw it. When Xerox decided it wasn't worth developing fully, they both decided to use it themselves.

<font color=green>I post so you don't have to!
9/11 - RIP</font color=green>

 

[Raystonn]

That is the difference between AMD's approach and Intel's approach. AMD must finish the product, packaging the two cores together. Then they test them as a unit. If one of the cores does not pass, they toss both cores in the garbage together. This wastes money.

Intel's new packaging allows cores to be tested individually. Once two cores are confirmed as having passed, they then package them together and test both together. You will never have a case of wasting a perfectly good core because its partner does not pass. This technology will no doubt be licensed to AMD eventually.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =

 

[Guest]

"but if *MD wants Intel to fab their cpu, maybe that can be worked out! "

Hah! I can just imagine it now:

Intel - Gee whiz AMD we just can't seem to get the yields up, we don't know what is going on. Oops, sorry. No really.

 

[Matisaro]

Rayy, however, the 2 cores are on a single die, with microelectronic level interconnections between them.(guesswork but if the things I have read on the hammer are true then yes) So in essence they are ONE core, you cannot seperate the two, also since they are the same core, they would perform faster than 2 cores in the same packaging. Instead of thinking of the hammer as 2 cores on one chip, think of it as one chip with 2 processing units inside. This is why it is not wasted money when one half of the hammer would fail.

[cheapshot] If intel is so worried about cost saving measures and are on the leading edge of such, why do we have to pay 5 times the price for their chips?[/cheapshot].

~Matisaro~
"The Cash Left In My Pocket,The BEST Benchmark"
~Tbird1.3@1.5~

 

[Raystonn]

"So in essence they are ONE core"

The end product may be thought of as a single 64-bit core, but it is truly manufactured by merging two separate 32-bit cores.


"you cannot seperate the two"

Alas, you can. They would be completely working 32-bit cores if they were not designed to be merged. The difference between the packaging of AMD and Intel is that Intel's cores would be testable before inserting them into the packaging. AMD's cores would be untestable until after being inserted together into the packaging. If 1 out of the 2 32-bit cores does not work then the whole unit will not work, and AMD will toss it out. This wastes one of the perfectly good 32-bit cores, increasing expenses.


"they would perform faster than 2 cores in the same packaging."

They _are_ two cores in the same packaging, merged together. Perhaps your definition of packaging is not the same as that of the industry? The two 32-bit cores are manufactured separately to start things off. What happens next is AMD merges them in the packaging and then tests them as a unit. If the 64-bit unit does not work, it gets tossed out. Intel would individually test the component 32-bit cores before inserting them into the packaging. This saves a great deal of money.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =

 

[FUGGER]

For someone who claims to work in a fab, you are clueless to how they are made and tested. let alone how they work.

You posted info a while back on defects in every chip made, yet you fail to use that information here.

WTG!

AMD will continue to copy Intel designs like they have always done. *cough*new organic package*cough*

I see your point, feeding second core zeros will be much faster than feeding a single core data. Brilliant observation.

 

[Matisaro]

Rayy, if I understand AMD's whitepapers corectly, the Hammer will be 2 cores on a single DIE, not package, you cannot seperate a die in half if one of the cores does not work. The memory controler will be on die as well.

If one of the cores is defective the whole thing is bad, they have interconnects between the cores ON DIE. You cannot seperate them. Bubbl packaging is very good, but the hammer design does not need it.
(BTW I am assuming this from both the amd whitepapers and the website which described hammer which was posted a week ago)

~Matisaro~
"The Cash Left In My Pocket,The BEST Benchmark"
~Tbird1.3@1.5~

 

[Matisaro]

If they were 2 identical cores packaged together like you say, which core would have the memory controler on it? No, the dual cores are in the same die.

The hammer core is 2 fully funtional cpu pipelines on the same DIE, this means they are processed together and the photo masks show a compelte 2 core design on them. They are not 32 bit cores put together in a package.

Packaging is the material they embed the chip in, in the standard process they attach gold leads to the bonding pads on the chip die. These leads attach to the pins which the cpu connects to the socket with. (for FUGGER.)

~Matisaro~
"The Cash Left In My Pocket,The BEST Benchmark"
~Tbird1.3@1.5~

 

[Raystonn]

"the Hammer will be 2 cores on a single DIE"

This is correct. That is what leads to the problem of having to throw out both cores when one is bad. Once you merge them onto the single die, that is it. You cannot remove either of them. Intel's packaging technology allows two cores on separate dies in the same packaging. Thus, each can be individually tested before being committed to the processor. The performance is the same no matter which method you choose to connect the cores. The performance could be increased by actually merging the two cores into a single core, but when they are two separate cores they will be just as fast whether they are on the same die or on separate dies in the same packaging. Thus with the new packaging you get the benefit of being able to individually test each core, you do not end up throwing out perfectly good cores because they were merged onto the same die as a bad core, and the performance is just as high. This is a win-win situation.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =

 

[Schmide]

Matisaro, I think you’re right on with your description of the Hammer.

Would this be a synopsis of the chip?

1 Memory Controller (cache)
1 Instruction Decoder
2 Fully functional Execution Units (cores) with Interconnects
1 Write Back Unit
1 Set of Interrupt Request Lines

What about the trace cache(s)? Is there one or two?

Schmide

 

[Matisaro]

I am not entirely sure about the trace caches.

Rayyston you are corect in your summary. I think however that having the 2 cores on a single die would be faster than hacing 2 cores in a single packaging, with both cores on a single die you can have high speed data interconnects built into the substrate, without having to have the chip send a single outside through the (albeit very short) copper datapath and into the other chip. Electical signals travel much more cleanly within a chip than they do when transmitted through outside copper wiring.

Intels new packaging is indeed very nice, but for the hammer concept it would not be very helpful. If one of the cores on the hammer fails , I would think of it as a totally failed chip regardless. The hammer diesize(2x athlon core guestimate) will still be smaller than a p4 and almost as small as a p4@.13 microns. This would be at .18, when the hammer shrinks to .13 it will be even smaller. With die size like that, yield is not as much of an impactor as it is with larger die. Therefore loss from single failed cores would not amount to much monetary loss. Also, I think that the hammers cores will not be able to be tested independantly at all, because they share the same IO system. Therefore when you place a finished hammer chip on a testing tool it will either pass or fail, it is best to think of the hammer as a single core with dual fully functional pipelines, than as 2 cores fused together. Much easier on the brain that way.

ps: all of the above on die size was speculation based on current athlon die size, hammer may be larger or smaller than 2x athlon core.

~Matisaro~
"The Cash Left In My Pocket,The BEST Benchmark"
~Tbird1.3@1.5~

 

[charliec2uk]

I remember reading this think when Intel were still making DRAM's. They were experimenting with a new design that only needed three gates for a memory cell or something. It wouldn't work. But by luck one person discovered by putting -15v across the chip for a bit, and them testing again as normal, they got the chips to work. This wasn't patented 'cos they wanted to keep it as secret as possible. (Only the paranoid survive).

Democracy Bernad, it must be stopped!

 

[Guest]

I believe that the Hammer actually doesn't have two cores. It is simply a misunderstanding, due to the limited information that AMD is (understandingly) supplying. Look at the following three year old PDF file about the Alpha EV6: <A HREF="http://www.compaq.com/alphaserver/download/ev6chip.pdf" target="_new">http://www.compaq.com/alphaserver/download/ev6chip.pdf</A>. The Hammer has a lot of features virtually copied from this old Alpha design. The EV6 has dual integer register files and funtional units for electrical reasons. Hooking too many units to one register file results in a bigger slower register file. It is this split register file that is fooling people into thinking there are two cores. Talking about the second core producing lower yields doesn't make sense, if there is no second core.

I have also read an article from one of the more more reputable publications (<A HREF="http://www.eetimes.com/story/OEG20011008S0027" target="_new">http://www.eetimes.com/story/OEG20011008S0027</A>) that shows that 1) the new package won't appear for 5-6 years and 2) Intel plans to include the northbridge, graphics processor, etc. in the package and not a second CPU. Something I think makes a lot more sense. The front side bus could go from 64 to 256 or 512 bits wide and blow any bandwidth limitations away. Putting multiple proccessors in a package would only make the existing heat problems even worse.

Patrick Ellis