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Raystonn i have a question ?

Last response: in CPUs
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October 25, 2001 10:26:26 PM

Well since you work for Intel i have a question that an Intel employshould know.

What are some the features on the P4 that are baised of the asynchronous cpu design ?

Since this the first chip of its kind that can support both asynchronous features and available to the public for home desktop users. Don't be surprized if you wtf is he talking about. Raystonn should know the answer or he isn't being very truthful.

Nice Nvidia and ATi users get a Cookie.... :smile: Yummy :smile:

More about : raystonn question

October 25, 2001 10:44:36 PM

Raystonn im not going to give you links to the answers so dont ask. Well its a challenge from me i hope you take it seriously it took me a long time to dig this up.

Nice Nvidia and ATi users get a Cookie.... :smile: Yummy :smile:
October 26, 2001 2:07:07 AM

First off, I do not see the need to 'prove' myself with some kind of challenge. If you do not believe what I say then so be it. I am not interested in finding out who does and does not believe what I say.

Second, you already know I cannot tell you anything that is confidential information. I can only repeat what has been released to the public. Thus, unless I find a link, there is not much I can legally say.

Third, the Pentium 4 does have some pieces of unclocked logic, the same technology that would be used in a clockless processor. Circuits that do not follow a main system clock are are also known as self-timed circuits. We are introducing asynchronous design into our processors slowly. Rather than go for the whole processor we are working our way up from smaller clockless modules within the design of a traditional processor. I cannot go into details on any information that has not been publicly released though.

Fourth, I am a software engineer. I am not one of the processor architects. Expecting me to know these details without looking them up on our intranet is pushing it. Most everything that is available on our intranet has the 'confidential' tag on it. So it is not very helpful in giving me information that I can actually share.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
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October 26, 2001 2:24:37 AM

Wouldn’t a clockless processor have some imaginary master clock frequency that all clocks on the system could synchronize to? The differences in synchronization would just be latencies between the clocks.

Schmide
October 26, 2001 2:31:05 AM

No. There is no master clock in a clockless processor. Every module (collection of components that perform some subtask) in the processor performs its task as quickly as possible. When there is no task for that particular module to perform, it is powered down. A clockless processor can be up to three times as fast as modern clocked processors while using half the power. The difficulty is in the design.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 2:34:43 AM

indeed... how the hell does one organise the output coherently if different parts of the cpu run at differing speeds.
too wierd for me

Religious wars are 2 groups of people fighting over who has the best imaginary friend.
October 26, 2001 2:43:47 AM

If I have separately clocked parts to a processor, and each unit runs at a different clock rate, then the product of all their clocks would be an <font color=yellow>imaginary</font color=yellow> frequency that all clocks could be scheduled to. I’m using a semantically challenged argument to prove a clock on an unclocked processor.

Schmide
October 26, 2001 2:49:06 AM

You can think of each subsection (module) of the processor as an independant server. When you send it some input, it creates some output for you and signals that the output is ready. You then read that output and move on to some other part of the process. For example, think of the internet. All the servers that are available are not operating in any synchronous fashion. Yet they are able to perform tasks for you and give you results when they are done. There is no set time in which results are expected. You are signalled (usually with a fresh page of results) when the data is available. You can then take that data and do whatever else you wish with it. Any server that is not currently being used does not have to be powered up processing anything. It can sit there idle in a power-saving mode.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 2:49:33 AM

LOL, that's cool.
How does a clockless processor determine how quickly it can perform a task?
Are there any of these clockless processors in operation?

"Ignorance is bliss, but I tend to get screwed over."
October 26, 2001 3:15:32 AM

hmmms. interesting.
that means in any given complex instruction set the cpu will run as fast as the slowest internal operation.

good job ray...
*grins*
whenever i see your name i think of 'ray' in ghostbusters.
hehe

Religious wars are 2 groups of people fighting over who has the best imaginary friend.
October 26, 2001 3:41:20 AM

Quote:
If I have separately clocked parts to a processor, and each unit runs at a different clock rate, then the product of all their clocks would be an imaginary frequency that all clocks could be scheduled to. I’m using a semantically challenged argument to prove a clock on an unclocked processor.

Each unit does not have a clock at all though. Each unit can be built with components that themselves are clockless.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 3:44:23 AM

"How does a clockless processor determine how quickly it can perform a task?"

In general it does not do this. If you need to know about the 'average' speed of an operation you can run it a few million times and average the results. Any particular instruction is not guaranteed to take the same amount of time every time you execute it.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 3:47:20 AM

"that means in any given complex instruction set the cpu will run as fast as the slowest internal operation."

Correct. This is instead of every operation being based off a clockrate that is tuned to the slowest step in the pipeline.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 3:55:01 AM

Hmmm...I still don't understand.

To the transistors just switch whenever they have inputs? How long does the switch take, and what factors is that speed dependent on? The quality of the fabrication?

"Ignorance is bliss, but I tend to get screwed over."
October 26, 2001 4:02:51 AM

The modules work when they get an input signal and send a signal when they have output. It would be entirely event-driven.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 4:10:58 AM

So each module has it's own clock, which can be set faster or slower than the other modules clocks depending on its characteristics?

"Ignorance is bliss, but I tend to get screwed over."
October 26, 2001 4:18:46 AM

if intel comes out with a clockless processor it will lose it only selling point megahz and gigahz think about that one
October 26, 2001 4:23:09 AM

Alright last chance to prove a clock on a clockless processor. Let there be a discrete number of operations preformed by the clocklesss processor. Each operation takes a discrete amount of time to complete. Their exists a divisor such that the timing of each operation can be represented by the product of an integer and that divisor. The effective clock rate is the inverse of that divisor.

Schmide

Thus the processor would effectively run at a very very large clock rate with a whole lot of wait states put in.
October 26, 2001 4:33:41 AM

That article has been posted on this form more times than meltdown has posted BS.

Interesting rant though.

~Matisaro~
"The Cash Left In My Pocket,The BEST Benchmark"
~Tbird1.3@1.5~
October 26, 2001 4:45:11 AM

No, modules do not have clocks. Nothing has a clock.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 4:48:44 AM

"Each operation takes a discrete amount of time to complete"

You never know how long an operation will take. Any number of modules may or may not be busy doing other things. Everything is event driven. Nothing waits for a clock.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 4:48:58 AM

[possibly dumb question] so if there's no clock to set the sync, would the limiting factor be the speed at which the slowest bus (channel, cable, whatever) can send the electrons? [/possibly dumb question]

no vestige of a beginning, no prospect of an end, when we all disintegrate, it'll all happen again.
October 26, 2001 4:49:29 AM

If the modules do not have clocks, what factors determine how fast the transistors in that module can switch from one state to another? Their size? The speed of light? Or am I missing something important?

"Ignorance is bliss, but I tend to get screwed over."
October 26, 2001 4:50:34 AM

About what in particular did you want me to comment. It is a large article.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 5:00:30 AM

If you can comment 'bout P4 in relation to P3 Tualin.
My understanding is that P4 is PR, healing ego wounds
by reaching 2Ghz first, after loosing 1Ghz race.




Breaking news: Intel hit by a SledgeHammer! AMD to blame! More in just a moment...
October 26, 2001 5:01:47 AM

The limiting factor would be how long it takes each module to do its part and forward the result to the next module. There would be no waiting around for clocks. When the data is ready, it is ready.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 5:03:35 AM

When a signal comes (the event) telling them to perform an operation, they do it. Thus, it is event-based.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 5:11:13 AM

The Tualatin was released because specific customers asked for it. The Pentium 3 is being phased out and should no longer be sold after this year. The Pentium 4 is the new flagship processor. It is designed to accel in the areas where most home users need the most performance, such as digital music, 3D gaming, digital imaging and video, and much more. The typical home user has indicated that current old processors are more than able to handle office applications, and so the focus was shifted to other areas.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 5:13:49 AM

Quote:
When a signal comes (the event) telling them to perform an operation, they do it. Thus, it is event-based.


...but a transistor can't change states instantaneously, there has to be a delay between one state and another doesn't there? I'm not talking about the module as a whole, but one single transistor inside it.

"Ignorance is bliss, but I tend to get screwed over."
October 26, 2001 5:15:46 AM

hmmmms... now ya got me thinking of possible parrallel-ism within a single chip.

instead of extreemly rapid switching from one task to another, which is what modern processors do i guess, if you had 2 tasks running, say one being mostly FPU calcs, the other Arithmetic, usually with just one task one parthway is very busy and the other is not.
concievably could u run both at once so both pathways are filled?
or is that a logistical nightmare

Is that a Northwoody in your pocket or are you just eXPited to see me?
October 26, 2001 5:31:33 AM

"but a transistor can't change states instantaneously, there has to be a delay between one state and another doesn't there"

When it receives the signal it changes state, signaling the next component.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 5:33:01 AM

Quote:
hmmmms... now ya got me thinking of possible parrallel-ism within a single chip

With every bit of parallel-ism you get a bunch of dependant-ism.
October 26, 2001 5:39:18 AM

(Discounting hyperthreading for a moment) multiple threads are currently implemented by the software, the operating system. All the processor knows is a list of commands (instructions) that it must perform. If it can tell that one command does not depend on the result of a previous command then it can perform both in parallel. This is already done in modern processors, but to much less of an extent.

You must explicitly design pipelines for each possible parallelism in a clocked processor. In a clockless processor, it is possible to perform instructions in parallel without explicitly designing a pipeline for it. But if you do not supply enough modules that perform a certain task, then anything that requires this task will be bottlenecked waiting on that module. So you still need to account for parallelism by providing multiple hardware units that perform many of the more common tasks.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 6:17:35 AM

Since the information is no longer restricted to a clock rate, does that mean that the limiting factor will now be the speed of the electron or (stream of electrons) making up that data?
October 26, 2001 6:54:19 AM

Here’s a weird one for ya.

I send a program to a clockless processor.

I time the amount of time it takes to process the code.

I do it again. It should execute the code in the same amount of time.

If it doesn’t, does that mean the processor has a varying performance?

If it does, you can thus measure the time for each operation and thus compute a divisor to determine the inferred clock rate.
October 26, 2001 7:20:03 AM

No, read above.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 7:24:31 AM

"It should execute the code in the same amount of time."

If absolutely nothing else varies in the system (i.e. system interrupts occur at the same place during execution of the same application, etc.) then it should take exactly the same amount of time to execute this code. However, since this will never happen, it will never take exactly the same amount of time to execute.


"... to determine the inferred clock rate."

There is no clockrate. There is only the average instructions per second rate. This figure varies depending on the set of instructions (application) you are executing.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 12:48:29 PM

Surley that kind of operation would be sensitive to cache limitations, or no more than standard processors.

But in the case of a clockless processor, each little subsystem does its own thing, right? So at the top of the hierachy you have some system that will allocate an operation to a subsystem. So the subsystem will go and fetch the uops from cache, process it, and return it to memory and send a flag to "High Command" that this result is available. So another system that needs that result can get it and so on. But do you still have the traditional components of alu's and such, but they are all in a little world of their own. A second question is that the band width to cache will have to be very high. I suppose that we could have a thousand subsystem all trying to do read/write operations into cache. Can a very enlightened and intelligent person sort out my drivel into coherent thoughts?

Charlie

Democracy Bernad, it must be stopped!
October 26, 2001 6:22:25 PM

"send a flag to 'High Command'"

It would likely send a signal to the next module in whatever dynamic pipeline is needed for that instruction to be processed.


"do you still have the traditional components of alu's and such, but they are all in a little world of their own"

The ALU is just a collection of components that are currently all working off a clock. You can design a set of components that work without any clock and perform the same task. You can then call it an ALU as well.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 10:40:11 PM

lol funny, what you have just described is the internet, Proxies, servers, connections, gateways.

hmm..was wondering if all computers evantually all go mainfraim subsystems(vax stations or what ever).

<font color=green>
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*K.I.S.S*
*(k)eep (I)t (S)imple (S)tupid*
*******
</font color=green>
October 26, 2001 11:12:34 PM

Except that it is an integrated circuit


Democracy Bernad, it must be stopped!
October 26, 2001 11:19:21 PM

integrated into what?
that is the question, 30 years ago computers were working as terminals from a mainframe, where all the processes were done.

<font color=green>
*******
*K.I.S.S*
*(k)eep (I)t (S)imple (S)tupid*
*******
</font color=green>
October 26, 2001 11:27:57 PM

Clockless processor's...an engineers dream and marketings worst nightmare :) 

I have a question, how do you syncronize the processor ( clockless) to the rest of the system that is clock dependent? Or would the memory busses etc need to be clockless as well?

Video editing?? Ha, I don't even own a camera!
October 26, 2001 11:44:25 PM

It would be best of course to have everything clockless. But you could make a unit that acted as a go-between. It could have a small amount of cache and accept data from the clockless processor whenever the data came. The unit would then transmit it to a clocked memory bus at the specified intervals, getting the data from the cache.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 26, 2001 11:50:08 PM

Yes, but then it would not be a truely clockless processor as it speed would be largely determined by the rate in which it could store and retrieve data, which was clockrate limited. I am thinking a very large on die cache might be more beneficial. Definatly an interesting topic of discussion but a ways off in the future I am afraid.

Video editing?? Ha, I don't even own a camera!
October 26, 2001 11:56:28 PM

This cache and translator would be on the MCH actually, not on the processor. The CPU would be clockless but the MCH would be a combination of both.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
October 27, 2001 1:41:08 PM

Quote:
Second, you already know I cannot tell you anything that is confidential information. I can only repeat what has been released to the public. Thus, unless I find a link, there is not much I can legally say.


Okay then Private Message or MSN "rcf84_r6_style@hotmail.com" me your answer. I fully know the answer and willing to share.

Nice Nvidia and ATi users get a Cookie.... :smile: Yummy :smile:
October 29, 2001 8:10:59 PM

Whats wrong raystonn... i have no private messages and no msn messages from you. Maybe you just dont know.

Nice Nvidia and ATi users get a Cookie.... :smile: Yummy :smile:
Anonymous
a b à CPUs
October 29, 2001 9:15:09 PM

Dude, what makes you think he is any more likely to PM you than post something here? You're basically asking him to commit what would be the corporate equivalent of treason.

Why don't you post the stupid links, and quit screwing around?
!